Y10S 438/00
Semiconductor device manufacturing: process
Y10S438/00 (Semiconductor device manufacturing: process) appears on 13,553 US grants and 5,705 published applications in this corpus.
Search patents in Y10S- Granted patents
- 13,553
- Published applications
- 5,705
- Assignees
- 1,828
- Inventors
- 17,155
- Latest grant
- 25 Nov 2025
Filings by year
| Year | Granted patents | Published applications |
|---|---|---|
| 1976 | 131 | 0 |
| 1977 | 100 | 0 |
| 1978 | 102 | 0 |
| 1979 | 94 | 0 |
| 1980 | 94 | 0 |
| 1981 | 110 | 0 |
| 1982 | 120 | 0 |
| 1983 | 119 | 0 |
| 1984 | 130 | 0 |
| 1985 | 139 | 0 |
| 1986 | 158 | 0 |
| 1987 | 178 | 0 |
| 1988 | 163 | 0 |
| 1989 | 206 | 0 |
| 1990 | 210 | 0 |
| 1991 | 243 | 0 |
| 1992 | 248 | 0 |
| 1993 | 361 | 0 |
| 1994 | 435 | 0 |
| 1995 | 434 | 0 |
| 1996 | 508 | 0 |
| 1997 | 538 | 0 |
| 1998 | 535 | 0 |
| 1999 | 620 | 0 |
| 2000 | 635 | 0 |
| 2001 | 682 | 262 |
| 2002 | 654 | 619 |
| 2003 | 623 | 606 |
| 2004 | 684 | 696 |
| 2005 | 580 | 632 |
| 2006 | 551 | 594 |
| 2007 | 500 | 467 |
| 2008 | 379 | 442 |
| 2009 | 448 | 338 |
| 2010 | 508 | 289 |
| 2011 | 438 | 219 |
| 2012 | 294 | 140 |
| 2013 | 126 | 94 |
| 2014 | 146 | 95 |
| 2015 | 135 | 67 |
| 2016 | 47 | 49 |
| 2017 | 38 | 22 |
| 2018 | 32 | 27 |
| 2019 | 27 | 17 |
| 2020 | 21 | 10 |
| 2021 | 13 | 6 |
| 2022 | 3 | 3 |
| 2023 | 3 | 3 |
| 2024 | 4 | 4 |
| 2025 | 6 | 4 |
By publication year. Applications have been published since 2001.
Subgroups
Granted patents
- Y10S 438/942Masking2,200
- Y10S 438/977Thinning or removal of substrate941
- Y10S 438/914Doping823
- Y10S 438/906Cleaning of wafer as interim step726
- Y10S 438/975Substrate or mask aligning feature600
- Y10S 438/981Utilizing varying dielectric thickness526
- Y10S 438/931Silicon carbide semiconductor509
- Y10S 438/905Cleaning of reaction chamber489
All 62 subgroupsShow fewer
- Y10S 438/933Germanium or silicon or ge-si on iii-v444
- Y10S 438/928Front and rear surface processing422
- Y10S 438/974Substrate surface preparation419
- Y10S 438/964Roughened surface404
- Y10S 438/978Forming tapered edges on substrate or adjacent layers383
- Y10S 438/958Passivation layer352
- Y10S 438/962Quantum dots and lines344
- Y10S 438/907Continuous processing309
- Y10S 438/938Lattice strain control or utilization302
- Y10S 438/94Laser ablative material removal298
- Y10S 438/926Dummy metallization290
- Y10S 438/909Controlled atmosphere263
- Y10S 438/935Gas flow control254
- Y10S 438/97Specified etch stop material254
- Y10S 438/954Making oxide-nitride-oxide device246
- Y10S 438/959Mechanical polishing of wafer242
- Y10S 438/96Porous semiconductor212
- Y10S 438/957Making metal-insulator-metal device201
- Y10S 438/976Temporary protective layer199
- Y10S 438/90Bulk effect device making179
- Y10S 438/911Differential oxidation and etching174
- Y10S 438/91Controlling charging state at semiconductor-insulator interface157
- Y10S 438/967Semiconductor on specified insulator154
- Y10S 438/963Removing process residues from vertical substrate surfaces151
- Y10S 438/973Substrate orientation151
- Y10S 438/902Capping layer145
- Y10S 438/965Shaped junction formation135
- Y10S 438/913Diverse treatments performed in unitary chamber130
- Y10S 438/927Electromigration resistant metallization126
- Y10S 438/936Graded energy gap110
- Y10S 438/983Zener diodes102
- Y10S 438/979Tunnel diodes100
- Y10S 438/937Hillock prevention99
- Y10S 438/98Utilizing process equivalents or options95
- Y10S 438/953Making radiation resistant device92
- Y10S 438/969Simultaneous formation of monocrystalline and polycrystalline regions92
- Y10S 438/93Ternary or quaternary semiconductor comprised of elements from three different groups89
- Y10S 438/904Charge carrier lifetime control85
- Y10S 438/982Varying orientation of devices in array81
- Y10S 438/903Catalyst aided deposition66
- Y10S 438/934Sheet resistance, i.e. dopant parameters66
- Y10S 438/961Ion beam source and generation55
- Y10S 438/971Stoichiometric control of host substrate composition50
- Y10S 438/901Capacitive junction46
- Y10S 438/966Selective oxidation of ion-amorphousized layer41
- Y10S 438/972Stored charge erasure38
- Y10S 438/932Boron nitride semiconductor36
- Y10S 438/956Making multiple wavelength emissive device35
- Y10S 438/955Melt-back29
- Y10S 438/941Loading effect mitigation26
- Y10S 438/939Langmuir-blodgett film utilization25
- Y10S 438/929Eutectic semiconductor22
- Y10S 438/912Displacing pn junction15
- Y10S 438/968Semiconductor-metal-semiconductor14
Recent patents
- Method for making ITO perovskite solar cells25 Nov 2025US 12,484,365 B2King Fahd University of Petroleum and Minerals
- Gas flow control during semiconductor fabrication4 Nov 2025US 12,463,065 B2Taiwan Semiconductor Manufacturing Company.Ltd
- Semiconductor patterning and resulting structures7 Oct 2025US 12,437,996 B2Taiwan Semiconductor Manufacturing Company.Ltd
- Method for forming patterned mask layer1 Apr 2025US 12,266,528 B2Taiwan Semiconductor Manufacturing Company.Ltd
- Method for producing a perovskite solar cell18 Mar 2025US 12,256,587 B2King Fahd University of Petroleum and Minerals
- Semiconductor patterning and resulting structures23 Oct 2025US 2025/0329533 A1Taiwan Semiconductor Manufacturing Company.Ltd
- Method for forming patterned mask layer19 Jun 2025US 2025/0201562 A1Taiwan Semiconductor Manufacturing Company.Ltd
- Methods of exposing conductive vias of semiconductor devices12 Jun 2025US 2025/0191972 A1Micron Technology, Inc.
- Method for making ito perovskite solar cells9 Jan 2025US 2025/0017027 A1King Fahd University of Petroleum and Minerals
- Self-forming, self-aligned barriers for back-end interconnects and methods of making same20 Jun 2024US 2024/0203786 A1Tahoe Research, Ltd.
Most cited
By later US patents
- Three dimensional structure memory1,560US 5,915,167 AElm Technology Corporation · 1999
- Method for producing compound thin films1,267US 4,058,430 A1977
- CVD Processing chamber1,003US 5,558,717 AAPPLIED Materials.Inc. · 1996
- Package of integrated circuits and vertical integration749US 6,322,903 B1Tru-Si Technologies, Inc. · 2001
- Single spacer process for multiplying pitch by a factor greater than two and related intermediate IC structures742US 7,611,980 B2Micron Technology, Inc. · 2009