Single spacer process for multiplying pitch by a factor greater than two and related intermediate IC structures
AssigneeMicron Technology, Inc.
InventorsDavid H. Wells, Mirzafer K. Abatchev
Life of this patent
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Abstract
Single spacer processes for multiplying pitch by a factor greater than two are provided. In one embodiment, n, where n≧2, tiers of stacked mandrels are formed over a substrate, each of the n tiers comprising a plurality of mandrels substantially parallel to one another. Mandrels at tier n are over and parallel to mandrels at tier n−1, and the distance between adjoining mandrels at tier n is greater than the distance between adjoining mandrels at tier n−1. Spacers are simultaneously formed on sidewalls of the mandrels. Exposed portions of the mandrels are etched away and a pattern of lines defined by the spacers is transferred to the substrate.
Claims18
A method for fabricating an integrated circuit, comprising:
- providing a first mandrel over a substrate, the first mandrel having a first width;
- providing a second mandrel substantially over the first mandrel, the second mandrel having a second width smaller than the first width;
- providing a layer of spacer material on the first and second mandrels;
- subjecting the layer of spacer material to a spacer etch, wherein the spacer etch simultaneously forms spacers on sidewalls of the first and second mandrels;
- selectively removing at least portions of the mandrels relative to the spacers to form a spacer pattern defined by the spacers;
- and
- processing the substrate through a mask defined by the spacer pattern.
Dependencies are inferred from the claim text.