Methods of exposing conductive vias of semiconductor devices

A method of exposing conductive vias of a semiconductor device, comprising:

• forming conductive vias extending from an active surface of a substrate, one or more of the conductive vias exhibiting a different length than other of the conductive vias;
• forming a barrier material over the conductive vias and the active surface of the substrate;
• conformally forming an isolation material over the barrier material;
• forming a self-planarizing isolation material over the isolation material, an exposed surface of the self-planarizing isolation material being substantially planar;
• removing a portion of the self-planarizing isolation material while an additional portion of the self-planarizing isolation material remains between the conductive vias;
• and
• removing a portion of the additional portion of the self-planarizing isolation material, the isolation material, and the barrier material to expose the conductive vias.

A method of exposing conductive vias of a semiconductor device, comprising:

• forming a barrier material over conductive vias on a substrate, one or more of the conductive vias exhibiting a different length than other of the conductive vias and the conductive vias separated from one another by a material of the substrate;
• forming a self-planarizing isolation material over the barrier material and between the conductive vias;
• removing a portion of the self-planarizing isolation material from over the barrier material while another portion of the self-planarizing isolation material remains between adjacent conductive vias;
• and
• removing portions of the isolation material and the barrier material to expose the conductive vias.