Y10S 438/938
Lattice strain control or utilization
Y10S438/938 (Lattice strain control or utilization) appears on 302 US grants and 159 published applications in this corpus.
Search patents in Y10S- Granted patents
- 302
- Published applications
- 159
- Assignees
- 114
- Inventors
- 515
- Latest grant
- 19 May 2015
Filings by year
| Year | Granted patents | Published applications |
|---|---|---|
| 1976 | 6 | 0 |
| 1977 | 1 | 0 |
| 1978 | 3 | 0 |
| 1979 | 4 | 0 |
| 1980 | 0 | 0 |
| 1981 | 3 | 0 |
| 1982 | 0 | 0 |
| 1983 | 2 | 0 |
| 1984 | 0 | 0 |
| 1985 | 4 | 0 |
| 1986 | 0 | 0 |
| 1987 | 1 | 0 |
| 1988 | 2 | 0 |
| 1989 | 8 | 0 |
| 1990 | 9 | 0 |
| 1991 | 6 | 0 |
| 1992 | 8 | 0 |
| 1993 | 13 | 0 |
| 1994 | 9 | 0 |
| 1995 | 5 | 0 |
| 1996 | 12 | 0 |
| 1997 | 18 | 0 |
| 1998 | 12 | 0 |
| 1999 | 7 | 0 |
| 2000 | 6 | 0 |
| 2001 | 5 | 1 |
| 2002 | 4 | 8 |
| 2003 | 10 | 10 |
| 2004 | 11 | 22 |
| 2005 | 9 | 21 |
| 2006 | 16 | 28 |
| 2007 | 20 | 17 |
| 2008 | 13 | 23 |
| 2009 | 25 | 10 |
| 2010 | 16 | 6 |
| 2011 | 16 | 6 |
| 2012 | 12 | 5 |
| 2013 | 2 | 0 |
| 2014 | 1 | 2 |
| 2015 | 3 | 0 |
By publication year. Applications have been published since 2001.
Recent patents
- Method of forming semiconductor device19 May 2015US 9,034,705 B2United Microelectronics Corp.
- Vertical group III-V nanowires on si, heterostructures, flexible arrays and fabrication13 Jan 2015US 8,932,940 B2The Regents of the University of California
- Semiconductor memory cell, device, and method for manufacturing the same6 Jan 2015US 8,927,963 B2Institute of Microelectronics, Chinese Academy of Sciences
- Asymmetric cyclic desposition etch epitaxy9 Dec 2014US 8,906,789 B2Taiwan Semiconductor Manufacturing Company.Ltd
- Technique for the growth of planar semi-polar gallium nitride3 Sep 2013US 8,524,012 B2Japan Science and Technology Agency
- Method of forming semiconductor device2 Oct 2014US 2014/0295629 A1United Microelectronics Corp.
- Asymmetric Cyclic Desposition Etch Epitaxy18 Sep 2014US 2014/0264348 A1Taiwan Semiconductor Manufacturing Company.Ltd
- Semiconductor memory cell, device, and method for manufacturing the same4 Oct 2012US 2012/0248503 A1Institute of Microelectronics, Chinese Academy of Sciences
- Method of fabrication of metal oxide semiconductor field effect transistor9 Aug 2012US 2012/0199849 A1United Microelectronics Corp.
- Structure with isotropic silicon recess profile in nanoscale dimensions2 Aug 2012US 2012/0193680 A1International Business Machines Corporation
Most cited
By later US patents
- Method of manufacturing a substrate using an SiGe layer600US 6,607,948 B1Kabushiki Kaisha Toshiba · 2003
- Technique for the growth of planar semi-polar gallium nitride267US 7,220,324 B2The Regents of the University of California · 2007
- Membrane dielectric isolation IC fabrication247US 5,354,695 A1994
- Membrane dielectric isolation IC fabrication223US 5,571,741 A1996
- Membrane dielectric isolation IC fabrication191US 5,840,593 AElm Technology Corporation · 1998