US 2012/0193680 A1 · STRUCTURE WITH ISOTROPIC SILICON RECESS PROFILE IN NANOSCALE DIMENSIONS

Abstract

A trench is formed by an anisotropic etch in a semiconductor material layer employing a masking layer, which can be gate spacers. In one embodiment, an adsorbed fluorine layer is provided at a cryogenic temperature only on vertical sidewalls of the semiconductor structure including the sidewalls of the trench. The adsorbed fluorine layer removes a controlled amount of the underlying semiconductor material once the temperature is raised above the cryogenic temperature. The trench can be filled with another semiconductor material to generate stress in the semiconductor material layer. In another embodiment, the semiconductor material is laterally etched by a plasma-based etch at a controlled rate while a horizontal portion of a contiguous oxide liner prevents etch of the semiconductor material from the bottom surface of the trench.

Claims20

Dependent claims

A semiconductor structure comprising:

a gate structure located on a semiconductor material layer comprising a first semiconductor material, said gate structure including a gate dielectric, a gate conductor, and a gate spacer;
a semiconductor material portion embedded in said semiconductor material layer, said semiconductor material portion comprising a second semiconductor material that is different from said first semiconductor material;
and
a non-planar interface region between said first semiconductor material and said second semiconductor material, wherein said non-planar interface region includes a first horizontal interface portion at a first depth from said gate dielectric, a second horizontal interface portion at a second depth from said gate dielectric, and a non-horizontal interface portion adjoined to said first horizontal interface portion and said second horizontal interface portion and underlying said gate spacer.

1 more element

A method of forming a semiconductor structure comprising:

forming a trench in a semiconductor material layer;
forming a contiguous semiconductor oxide liner on sidewalls and a bottom surface of said trench;
exposing sidewall surfaces of said trench by removing vertical portions of said contiguous semiconductor oxide liner while a remaining horizontal semiconductor oxide portion of said contiguous semiconductor oxide liner overlies a portion of said semiconductor material layer located underneath said trench, wherein said remaining horizontal semiconductor oxide portion includes a top surface that contiguously extends from one of said sidewall surfaces to another of said sidewall surfaces after said sidewall surfaces are exposed;
and
laterally etching said sidewall surfaces of said trench while said remaining horizontal semiconductor oxide portion covers said portion of said semiconductor material layer located underneath said trench and a portion of said remaining horizontal semiconductor oxide portion is exposed within said trench.

2 more elements

Dependencies are inferred from the claim text.

Structure with isotropic silicon recess profile in nanoscale dimensions

Life of this patent

Structure with isotropic silicon recess profile in nanoscale dimensions

Life of this patent

Abstract

Claims20