US 2012/0199849 A1 · METHOD OF FABRICATION OF METAL OXIDE SEMICONDUCTOR FIELD EFFECT TRANSISTOR

Abstract

A method of fabrication of a metal oxide semiconductor field effect transistor includes first providing a substrate on which a gate structure is formed. Afterwards, a portion of the substrate is removed to form a first recess in the substrate at both ends of the gate structure. Additionally, a source/drain extension layer is deposited in the first recess and a number of spacers are formed at both ends of the gate structure. Subsequently, a portion of the source/drain extension and the substrate are removed to form a second recess in the source/drain extension and a portion of the substrate outside of the spacer. In addition, a source/drain layer is deposited in the second recess. Because the source/drain extension and the source/drain layer have specific materials and structures, short channel effect is improved and the efficiency of the metal oxide semiconductor field effect transistor is improved.

Claims16

Dependent claims

A metal oxide semiconductor field effect transistor, comprising:

a substrate;
a gate structure, disposed on the substrate;
a spacer, disposed on a side wall of the gate structure;
a source/drain extension layer, disposed in the substrate and below the spacer;
a source/drain layer, disposed in the substrate and outside of the spacer, wherein the depth of the source/drain layer is larger than the depth of the source/drain extension layer;
and
a dopant diffusion barrier layer, disposed directly under the source/drain extension layer and in a side of the source/drain extension layer near the gate structure;
wherein an entire of the source/drain layer is comprised of a strained material comprising two different atoms.

5 more elements

Dependencies are inferred from the claim text.

Facts

Application

13/446,124Filed 13 Apr 2012

Priority

26 Apr 2006

Published

9 Aug 2012

Term ends

Not estimatedThe source records don’t support an estimate.

Classification11 codes

H10D 30/797
Arrangements for exerting mechanical stress on the crystal lattice of the channel regions: being in source or drain regions, e.g. SiGe source or drain
H10D 30/608
Having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs: having non-planar bodies, e.g. having recessed gate electrodes
H10D 62/021
Manufacture or treatment: forming source or drain recesses by etching e.g. recessing by etching and then refilling
H10D 64/021
Manufacture or treatment: using multiple gate spacer layers, e.g. bilayered sidewall spacers

Method of fabrication of metal oxide semiconductor field effect transistor

Life of this patent

Method of fabrication of metal oxide semiconductor field effect transistor

Life of this patent

Abstract

Claims16