Asymmetric Cyclic Desposition Etch Epitaxy
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsChun Hsiung Tsai, Yi-Fang Pai, Chien-Chang Su, Tzu-Chun Tseng, Meng-Yueh Liu
Life of this patent
Estimating the term…
Loading patent…
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsChun Hsiung Tsai, Yi-Fang Pai, Chien-Chang Su, Tzu-Chun Tseng, Meng-Yueh Liu
Estimating the term…
The present disclosure relates to a method of forming an epitaxial layer through asymmetric cyclic deposition etch (CDE) epitaxy. An initial layer growth rate of one or more cycles of the CDE process are designed to enhance a crystalline quality of the epitaxial layer. A growth rate of the epitaxial material may be altered by adjusting a flow rate of one or more silicon-containing precursors within a processing chamber wherein the epitaxial growth takes place. An etch rate may also be altered by adjusting a temperature or partial pressure of one or more vapor etchants, or the temperature within the processing chamber. In some embodiments, an initial layer thickness that is greater than a critical thickness of the epitaxial material for strain relaxation is achieved with a low growth rate, followed by a high growth rate for the remainder of epitaxial growth. Other methods are also disclosed.
A method to form an epitaxial layer on a substrate within a processing chamber, comprising:
A method to form an epitaxial layer within a recess, comprising:
A field-effect transistor (FET) formed on a substrate, comprising:
Dependencies are inferred from the claim text.