G01R 31/318533
Using scanning techniques
Official title: {using scanning techniques, e.g. LSSD, Boundary Scan, JTAG}
G01R31/318533 (Using scanning techniques) appears on 5,191 US grants and 4,140 published applications in this corpus.
Search patents in G01R- Granted patents
- 5,191
- Published applications
- 4,140
- Assignees
- 700
- Inventors
- 6,323
- Latest grant
- 6 Oct 2026
Filings by year
| Year | Granted patents | Published applications |
|---|---|---|
| 1976 | 3 | 0 |
| 1977 | 6 | 0 |
| 1978 | 3 | 0 |
| 1979 | 1 | 0 |
| 1980 | 2 | 0 |
| 1981 | 4 | 0 |
| 1982 | 5 | 0 |
| 1983 | 1 | 0 |
| 1984 | 7 | 0 |
| 1985 | 15 | 0 |
| 1986 | 17 | 0 |
| 1987 | 27 | 0 |
| 1988 | 21 | 0 |
| 1989 | 31 | 0 |
| 1990 | 27 | 0 |
| 1991 | 32 | 0 |
| 1992 | 42 | 0 |
| 1993 | 34 | 0 |
| 1994 | 50 | 0 |
| 1995 | 69 | 0 |
| 1996 | 96 | 0 |
| 1997 | 104 | 0 |
| 1998 | 123 | 0 |
| 1999 | 98 | 0 |
| 2000 | 94 | 0 |
| 2001 | 114 | 28 |
| 2002 | 109 | 148 |
| 2003 | 139 | 165 |
| 2004 | 163 | 186 |
| 2005 | 131 | 234 |
| 2006 | 172 | 213 |
| 2007 | 210 | 241 |
| 2008 | 201 | 234 |
| 2009 | 241 | 217 |
| 2010 | 260 | 207 |
| 2011 | 272 | 198 |
| 2012 | 172 | 167 |
| 2013 | 217 | 201 |
| 2014 | 216 | 197 |
| 2015 | 204 | 178 |
| 2016 | 186 | 164 |
| 2017 | 166 | 154 |
| 2018 | 148 | 131 |
| 2019 | 166 | 119 |
| 2020 | 122 | 110 |
| 2021 | 132 | 130 |
| 2022 | 116 | 103 |
| 2023 | 140 | 125 |
| 2024 | 128 | 126 |
| 2025 | 100 | 100 |
| 2026 | 54 | 64 |
By publication year. Applications have been published since 2001. 2026 runs to 8 Oct.
Subgroups
Granted patents
- G01R 31/318544Scanning methods, algorithms and patterns1,256
- G01R 31/318536Scan chain arrangements1,147
- G01R 31/318555Control logic897
- G01R 31/318572Input/output interfaces897
- G01R 31/318558Addressing or selecting of subparts of the device under test842
- G01R 31/318541Scan latches or cell details792
- G01R 31/318552Clock circuits details602
- G01R 31/318594Timing aspects510
Recent patents
- I3C error states test strategy6 Oct 2026US 12,754,235 B2Microchip Technology Incorporated
- Data correction and phase optimization in high-speed receivers6 Oct 2026US 12,754,237 B2Diodes Incorporated
- Chip testing method and apparatus15 Sep 2026US 12,736,583 B2Xiamen Industrial Technology Research Institute Co., Ltd.
- High performance data latching using an energy efficient clocked latch topology15 Sep 2026US 12,738,929 B2International Business Machines Corporation
- State clearing of internal memory and flip-flops of a system using built-in test and scan circuitry8 Sep 2026US 12,730,940 B2Microsoft Technology Licensing, LLC
- Wrapper Cell Design and Built-In Self-Test Architecture for 3DIC Test and Diagnosis8 Oct 2026US 2026/0309778 A1Taiwan Semiconductor Manufacturing Company.Ltd
- Jtag-based soc design verification on emulation1 Oct 2026US 2026/0299020 A1Microsoft Technology Licensing, LLC
- Multi-phase synchronized method for lane margining1 Oct 2026US 2026/0299021 A1SK hynix Inc.
- Testing large-scale electronic systems constituted of many functional blocks1 Oct 2026US 2026/0299023 A1Krivya Semicon Private Limited
- System for Directional Scan Access and Method for Directional Scan Testing Thereof24 Sep 2026US 2026/0287656 A1
Most cited
By later US patents
- Correlation of electrical test data with physical defect data433US 6,950,771 B1Xilinx, Inc. · 2005
- Method to locate logic errors and defects in digital circuits273US 7,296,201 B2DAFCA, Inc. · 2007
- Emulation devices, systems and methods utilizing state machines263US 5,329,471 ATexas Instruments Incorporated · 1994
- Series maxium/minimum function computing devices, systems and methods238US 5,072,418 ATexas Instruments Incorporated · 1991
- Apparatus for at-speed testing, in inter-domain mode, of a multi-clock-domain digital integrated circuit according to BIST or SCAN techniques226US 8,862,955 B2STMicroelectronics S,r.l. · 2014