Chip testing method and apparatus
AssigneeXiamen Industrial Technology Research Institute Co., Ltd.
InventorsYonghong Huang, Juilung Chen, Yongbo Liu, Huayi Liu, Wenjie Su
Life of this patent
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Abstract
A chip testing method and apparatus are provided, and the method includes: providing a plurality of chips, each of the chips including an input pin, an output pin, and a state machine circuit; connecting the input pin of each of the chips to a same input start module which outputs a start signal to each of the chips to start the state machine circuits; configuring the state machine circuit of each of the chips to output a test excitation to test the chips and obtain a test result; and connecting the output pin of each of the chips to a same testing module which outputs the test result of each of the chips.
Claims10
A chip testing method, comprising:
- providing a plurality of chips, wherein each of the plurality of chips comprises an input pin, an output pin, and a state machine circuit;
- connecting the input pin of each of the plurality of chips to an identical input start module, wherein the identical input start module outputs a start signal to each of the plurality of chips to start the state machine circuits;
- configuring the state machine circuit of each of the plurality of chips to output a test excitation to test the plurality of chips and obtain a test result;
- and
- connecting the output pin of each of the plurality of chips to an identical testing module, wherein the identical testing module outputs the test result of each of the plurality of chips.
A chip testing apparatus, comprising:
- a plurality of chips, wherein each of the plurality of chips comprises an input pin, an output pin, and a state machine circuit;
- an input start module connected to the input pin of each of the plurality of chips, and configured to output a start signal to each of the plurality of chips to start the state machine circuits;
- the state machine circuit of each of the plurality of chips configured to output a test excitation to test the plurality of chips and obtain a test result;
- and
- a testing module connected to the output pin of each of the plurality of chips, and configured to output the test result of each of the plurality of chips.
Dependencies are inferred from the claim text.