G01R 31/3185
Reconfiguring for testing
Official title: Reconfiguring for testing, e.g. LSSD, partitioning
G01R31/3185 (Reconfiguring for testing) appears on 6,762 US grants and 5,089 published applications in this corpus.
Search patents in G01R- Granted patents
- 6,762
- Published applications
- 5,089
- Assignees
- 927
- Inventors
- 8,682
- Latest grant
- 6 Oct 2026
Filings by year
| Year | Granted patents | Published applications |
|---|---|---|
| 1976 | 8 | 0 |
| 1977 | 10 | 0 |
| 1978 | 4 | 0 |
| 1979 | 2 | 0 |
| 1980 | 7 | 0 |
| 1981 | 9 | 0 |
| 1982 | 8 | 0 |
| 1983 | 6 | 0 |
| 1984 | 11 | 0 |
| 1985 | 30 | 0 |
| 1986 | 23 | 0 |
| 1987 | 44 | 0 |
| 1988 | 37 | 0 |
| 1989 | 52 | 0 |
| 1990 | 53 | 0 |
| 1991 | 47 | 0 |
| 1992 | 60 | 0 |
| 1993 | 55 | 0 |
| 1994 | 68 | 0 |
| 1995 | 100 | 0 |
| 1996 | 124 | 0 |
| 1997 | 137 | 0 |
| 1998 | 176 | 0 |
| 1999 | 143 | 0 |
| 2000 | 142 | 0 |
| 2001 | 166 | 40 |
| 2002 | 156 | 192 |
| 2003 | 199 | 226 |
| 2004 | 238 | 253 |
| 2005 | 197 | 284 |
| 2006 | 235 | 253 |
| 2007 | 277 | 290 |
| 2008 | 257 | 294 |
| 2009 | 299 | 259 |
| 2010 | 326 | 250 |
| 2011 | 328 | 240 |
| 2012 | 195 | 193 |
| 2013 | 251 | 233 |
| 2014 | 252 | 232 |
| 2015 | 243 | 222 |
| 2016 | 219 | 200 |
| 2017 | 207 | 173 |
| 2018 | 173 | 157 |
| 2019 | 200 | 146 |
| 2020 | 150 | 138 |
| 2021 | 162 | 168 |
| 2022 | 146 | 138 |
| 2023 | 182 | 154 |
| 2024 | 160 | 145 |
| 2025 | 124 | 126 |
| 2026 | 64 | 83 |
By publication year. Applications have been published since 2001. 2026 runs to 8 Oct.
Subgroups
Granted patents
Recent patents
- I3C error states test strategy6 Oct 2026US 12,754,235 B2Microchip Technology Incorporated
- Data correction and phase optimization in high-speed receivers6 Oct 2026US 12,754,237 B2Diodes Incorporated
- Chip testing method and apparatus15 Sep 2026US 12,736,583 B2Xiamen Industrial Technology Research Institute Co., Ltd.
- High performance data latching using an energy efficient clocked latch topology15 Sep 2026US 12,738,929 B2International Business Machines Corporation
- State clearing of internal memory and flip-flops of a system using built-in test and scan circuitry8 Sep 2026US 12,730,940 B2Microsoft Technology Licensing, LLC
- Wrapper Cell Design and Built-In Self-Test Architecture for 3DIC Test and Diagnosis8 Oct 2026US 2026/0309778 A1Taiwan Semiconductor Manufacturing Company.Ltd
- Jtag-based soc design verification on emulation1 Oct 2026US 2026/0299020 A1Microsoft Technology Licensing, LLC
- Multi-phase synchronized method for lane margining1 Oct 2026US 2026/0299021 A1SK hynix Inc.
- Testing large-scale electronic systems constituted of many functional blocks1 Oct 2026US 2026/0299023 A1Krivya Semicon Private Limited
- System for Directional Scan Access and Method for Directional Scan Testing Thereof24 Sep 2026US 2026/0287656 A1
Most cited
By later US patents
- User programmable integrated circuit interconnect architecture and test method471US 4,758,745 AActel Corporation · 1988
- Correlation of electrical test data with physical defect data433US 6,950,771 B1Xilinx, Inc. · 2005
- Source synchronous link integrity validation423US 6,965,648 B1Sun Microsystems, Inc. · 2005
- Programmable interconnect architecture399US 4,873,459 AActel Corporation · 1989
- FPGA having logic cells configured by SRAM memory cells and interconnect configured by antifuses334US 5,744,979 AXilinx, Inc. · 1998