Correlation of electrical test data with physical defect data

A method for testing a semiconductor chip, comprising:

• inspecting the semiconductor chip for defects and storing an inspection data set that identifies a first set of physical locations associated with defects detected during inspection;
• testing circuit paths on the semiconductor chip, and storing a test data set that includes one or more identifiers associated with failing circuitry in the semiconductor chip;
• determining a second set of physical locations of defects described by the test data set from the one or more identifiers of failing circuitry, hierarchical relationships between blocks of a design, and placement information associated with the blocks, wherein each of the one or more identifiers is associated with at least one of the blocks;
• and
• identifying correspondences between physical locations in the inspection data set and the second set of physical locations.

An apparatus for analyzing defect data produced in testing a chip from a design, comprising:

• means for inputting a first data set that identifies a first set of physical locations associated with defects detected during fabrication of the chip;
• means for inputting a second test data set that includes one or more identifiers associated with failing circuitry in the chip;
• means for determining a second set of physical locations from the one or more identifiers of failing circuitry, hierarchical relationships between blocks of the design, and placement information associated with the blocks, wherein each of the one or more identifiers is associated with at least one of the blocks;
• and
• means for identifying correspondences between physical locations in the first data set and the second set of physical locations.