High performance data latching using an energy efficient clocked latch topology

An apparatus comprising:

• a first latch including:
• a functional clock input node configured to receive a functional clock signal that cycles between an active phase and an inactive phase;
• a scan clock input node configured to receive a scan clock signal;
• a functional data input node configured to receive an input signal indicative of a binary data value;
• a scan port configured to receive scan data;
• a latch circuit comprising a plurality of gates, the latch circuit configured to:
• latch the binary data value based on the functional clock signal being in the active phase;
• and
• output the binary data value until a different data value is received by the latch circuit;
• wherein the plurality of gates includes a plurality of clocked gates and a plurality of non-clocked gates, the plurality of clocked gates including a maximum of three clocked gates;
• wherein the latch circuit preserves a static state in the plurality of non-clocked gates across clock transitions as long as the binary data value at the functional data input node matches the latched binary data value;
• wherein the scan port is further configured to input the scan data into the latch circuit based on the scan clock signal;
• and
• wherein the plurality of gates includes:
• a first NFET stack connected between a first internal node and a ground reference, the first NFET stack including a NFET gated by the functional clock signal, and
• a PFET connected between a power reference and the first internal node, wherein the PFET is gated by the functional clock signal.

A method of a latch using a low power latch topology, the method comprising:

• receiving, at a functional clock input node, a functional clock signal that periodically transitions between an active phase and an inactive phase;
• receiving, at a data input node, an input signal indicative of a binary data value;
• latching, by a latch circuit, the binary data value based on the functional clock signal being in the active phase;
• and
• outputting the binary data value until a different data value is received at the data input node;
• wherein the latch circuit includes a plurality of gates including a plurality of clocked gates and a plurality of non-clocked gates, the plurality of clocked gates including a maximum of three clocked gates;
• wherein the latch circuit preserves a static state in the plurality of non-clocked gates across clock transitions as long as the data value at the data input node matches the latched data value;
• and
• wherein the plurality of gates includes:
• a NFET stack connected between a first internal node and a ground reference, the first NFET stack including a NFET gated by the functional clock signal, and
• a PFET connected between a power reference and the first internal node, wherein the PFET is gated by the functional clock signal.