State clearing of internal memory and flip-flops of a system using built-in test and scan circuitry

A method for state clearing of internal memories and flip-flops of a system for a security reason, the method comprising:

• a security processor fetching memory built-in self-test (MBIST) data, validating the MBIST data, and providing the validated MBIST data to an internal field-test (IFT) controller associated with the system such that the IFT controller can drive the validated MBIST data via an internal joint test action group (IJTAG) network to respective MBIST controllers within the system;
• the security processor fetching scan data, validating the scan data, and providing the validated scan data to the IFT controller such that the IFT controller can drive the validated scan data via a scan network to respective embedded deterministic test (EDT) controllers within the system;
• upon receiving pertinent MBIST data, each of the respective MBIST controllers, within the system, state clearing respective internal memories by writing the pertinent MBIST data into the respective internal memories;
• and
• upon receiving pertinent scan data, each of the respective EDT controllers, within the system, state clearing respective flip-flops by writing the pertinent scan data into the respective flip-flops.

A system comprising:

• a plurality of memory built-in self-test (MBIST) controllers within the system coupled to respective internal memories within the system;
• a plurality of embedded deterministic test (EDT) controllers within the system coupled to respective flip-flops within the system;
• a security processor, for a security reason, configured to:
• (1) fetch memory built-in test (MBIST) data, validate the MBIST data and provide the validated MBIST data to an internal field-test (IFT) controller associated with the system such that the IFT controller can drive the validated MBIST data via an internal joint test action group (IJTAG) network to respective MBIST controllers within the system, and (2) fetch scan data, validate the scan data, and provide the validated scan data to the IFT controller such that the IFT controller can drive the validated scan data via a scan network to respective EDT controllers within the system;
• and
• wherein:
• (1) each respective MBIST controller, within the system, configured to state clear respective internal memories by writing pertinent MBIST data into the respective internal memories, and (2) each respective EDT controller, within the system, configured to state clear respective flip-flops by writing pertinent scan data into the respective flip-flops.