Wrapper Cell Design and Built-In Self-Test Architecture for 3DIC Test and Diagnosis
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsAnshuman CHANDRA, Sandeep Kumar Goel
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Abstract
Systems, methods, and devices are described herein for performing intra-die and inter-die tests of one or more dies of an integrated circuit. A cell of an integrated circuit includes a data register, an I/O pad, and a first multiplexer. The data register is configured to output a signal. The I/O pad is coupled to the data register and configured to receive and buffer the signal. The first multiplexer is coupled to the I/O pad and the data register. The multiplexer is configured to selectively output either the buffered signal or the signal based on whether a scan mode or a functional mode is enabled.
Claims20
A cell comprising:
- a selector circuit coupled to an input/output (I/O) pad and a data register, the selector circuit configured to selectively output either a signal from the data register or a buffered signal from the I/O pad.
An integrated circuit comprising:
- a first die including a first cell having a first selector circuit, a first data register, and a first input/output (I/O) pad;
- and
- a second die coupled to the first die.
A method of testing one or more dies, the method comprising:
- receiving, by a data register of a die, data including a pre-determined test pattern;
- and
- providing, via a loopback path formed by an input/output (I/O) pad and a selector circuit, the buffered pre-determined test pattern back to the data register.
Dependencies are inferred from the claim text.