Jtag-based soc design verification on emulation

One or more physically manufactured computer-readable storage media, encoding computer-executable instructions for executing on a computer system a computer process, the computer process comprising:

• generating a register database, wherein the register database is configured to store one or more parameters of a plurality of registers, the plurality of registers representing the registers for a plurality of functional components on a system on chip (SoC);
• receiving a design verification flow for verifying one or more of the plurality of functional components on the SOC;
• generating a design verification script based on design verification flow;
• converting the design verification script into a series of JTAG transactions;
• and
• executing the series of JTAG transactions using a JTAG transactor.

A system comprising:

• memory;
• one or more processing units;
• and
• a system on chip (SOC) design verification and emulation system stored in the memory and executable by the one or more processor units, the SOC design verification and emulation system encoding computer-executable instructions on the memory for executing on the one or more processor units a computer process, the computer process comprising:
• generating a register database, wherein the register database is configured to store one or more parameters of a plurality of registers, the plurality of registers representing the registers for a plurality of functional components on a system on chip (SoC);
• receiving a design verification flow for verifying one or more of the plurality of functional components on the SOC;
• generating a design verification script based on design verification flow;
• converting the design verification script into a series of JTAG transactions;
• and
• executing the series of JTAG transactions using a JTAG transactor.