Data correction and phase optimization in high-speed receivers

A method for performing data correction, comprising:

• receiving a bitstream from an analog-to-digital converter (ADC), the bitstream comprising a plurality of data bits and a corresponding plurality of data sign bits;
• determining whether to correct a data sign bit of the plurality of data sign bits;
• responsive to determining the data sign bit of the plurality of data sign bits is to be corrected, flipping the data sign bit of the plurality of data sign bits;
• and
• providing the plurality of data sign bits, including the flipped data sign bit, to a decision feedback equalizer (DFE).

A system for performing phase optimization, comprising:

• data correction circuitry configured to:
• receive a bitstream from an analog-to-digital converter (ADC), the bitstream comprising a plurality of data bits and a corresponding plurality of data sign bits;
• determine a current error value associated with the bitstream;
• determine whether to perform a phase adjustment of a sampling clock based on the current error value;
• responsive to determining that a phase adjustment is to be performed, determine a phase offset to be applied to the sampling clock;
• and
• provide the determined phase offset to a clock and data recovery (CDR) block, wherein providing the determined phase offset to the CDR block causes an edge of the sampling clock to be moved toward alignment with a center of a data bit waveform associated with a data bit of the plurality of data bits.

A method for performing phase optimization, comprising:

• receiving a bitstream from an analog-to-digital converter (ADC), the bitstream comprising a plurality of data bits and a corresponding plurality of data sign bits;
• determining a current error value associated with the bitstream;
• determining whether to perform a phase adjustment of a sampling clock based on the current error value;
• responsive to determining that a phase adjustment is to be performed, determining a phase offset to be applied to the sampling clock;
• and
• providing the determined phase offset to a clock and data recovery (CDR) block, wherein providing the determined phase offset to the CDR block causes an edge of the sampling clock to be moved toward alignment with a center of a data bit waveform associated with a data bit of the plurality of data bits.