Source synchronous link integrity validation

A method comprising:

• generating a first transition on a first line of a source synchronous link to cause a first reflection on said first line;
• subsequently generating a first crossing pulse on said first line and generating a second crossing pulse on a second line of said source synchronous link, said generating said second crossing pulse performed concurrent with said generating said first crossing pulse, said second crossing pulse having an opposite polarity of said first crossing pulse;
• receiving said first crossing pulse and said second crossing pulse in a receiving circuit coupled to said first line and to said second line;
• generating a second transition on said first line to cause a second reflection on said first line subsequent to said generating said first crossing pulse;
• subsequently generating a third crossing pulse on said first line, wherein a first number of data transfers on said first line between said first reflection and said first crossing pulse differs from a second number of data transfers on said first line between said second reflection and said third crossing pulse;
• and
• verifying that signals on said first line and said second line are correctly received in said receiving circuit.

A system comprising:

• a source synchronous link including at least a first line and a second line;
• a first circuit coupled to transmit on said source synchronous link;
• a second circuit coupled to receive on said source synchronous link;
• wherein said first circuit is configured to transmit a first transition for generating a first reflection on said first line and to transmit a subsequent first crossing pulse on said first line, and wherein said first circuit is configured to transmit a second crossing pulse on said second line, said second crossing pulse transmitted concurrent with said first crossing pulse and having an opposite polarity of said first crossing pulse, and wherein said second circuit is configured to verify that signals on said first line and said second line are correctly received;
• a second source synchronous link including at least a third line and a fourth line;
• a third circuit coupled to transmit on said second source synchronous link;
• a fourth circuit coupled to receive on said second source synchronous link;
• and
• wherein said third circuit is configured to transmit a second transition for generating a second reflection on said third line and to transmit a subsequent third crossing pulse on said first line, and wherein said third circuit is configured to transmit a fourth crossing pulse on said fourth line, said fourth crossing pulse transmitted concurrent with said third crossing pulse and having an opposite polarity of said third crossing pulse, and wherein said fourth circuit is configured to receive said fourth crossing pulse and to verify that said fourth crossing pulse is correctly received.

A system comprising:

• a source synchronous link including at least a first line and a second line;
• a first circuit coupled to transmit on said source synchronous link;
• and
• a second circuit coupled to receive on said source synchronous link;
• wherein said first circuit is configured to transmit a first transition for generating a first reflection on said first line and to transmit a subsequent first crossing pulse on said first line, and wherein said first circuit is configured to transmit a second crossing pulse on said second line, said second crossing pulse transmitted concurrent with said first crossing pulse and having an opposite polarity of said first crossing pulse, and wherein said second circuit is configured to verify that signals on said first line and said second line are correctly received;
• and wherein said first circuit is further configured to transmit a second transition for generating a second reflection on said first line subsequent to transmitting said first crossing pulse, and wherein said first circuit is further configured to transmit a third crossing pulse on said first line, wherein a first number of data transfers on said first line between said first transition and said first crossing pulse differs from a second number of data transfers on said first line between said second transition and said third crossing pulse.