I3C error states test strategy

A method for testing an I3C device, the method comprising:

• receiving, at a start/stop detection logic block, a serial data line (SDA) signal and a serial clock line (SCL) signal;
• outputting, from the start/stop detection logic block, a start detection signal and a stop detection signal;
• receiving, at a SCL counter block, the SCL signal and the start and stop detection signals;
• outputting, from the SCL counter block, a SCL count value, a SCL positive edge detection signal, and a SCL negative edge detection signal;
• receiving, at a SDA inversion logic block, the SCL count value, a SCL programmed count value, and the SCL positive and negative edge detection signals;
• outputting, from the SDA inversion block, a SDA invert enable signal based on a comparison of the SCL count value and the SCL programmed count value;
• receiving, at a multiplexer, the SDA signal, an inverted SDA signal, and the SDA invert enable signal;
• and
• outputting, from the multiplexer, the SDA signal or the inverted SDA signal based on the SDA invert enable signal.