US 7,296,201 B2Granted

Method to locate logic errors and defects in digital circuits

AssigneeDAFCA, Inc.

InventorMiron Abramovici

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Abstract

When, in the course of an integrated circuit's functional test an assertion fires at clock k, the operational clock is stopped, the sequence is reapplied to capture inputs to the assertion circuit that fired, signals within the assertion circuit are computed, and the error is backtraced. Once one or more inputs of the assertion circuit are identified as potentially the source of the error, the process of backtracing is performed for each such input. When the input that is potentially the source of the error emanates from a memory circuit, the fanin cone of the memory circuit is identified and the process of backtracing through the last-identified fanin cone is undertaken for clock k−1. This is repeated iteratively until either a module of the integrated circuit is found to be the source of the error, or the error is extended to inputs of the SoC.

Claims20

Dependent claims

A method for testing a circuit when in the course of said testing information is developed that indicates that an error is present in one or more signals Sj,l(k), where j is an index that distinguishes different ones of said signals, l is a level indicator that is initially set at 0, and k indicates a number of operational clock periods following a given condition when said error signals appear, said method starting with a variable m equal to k, and comprising the steps of:

for at least one of the signals Sj,i(m),
(a) identifying an associated fanin cone;
(b) re-testing said circuit, and capturing input signals of said fanin cone;
(c) processing information about said fanin cone to
(1) identify an error within said fanin cone, or
(2) identify a collection of input signals of said fanin code that potentially are at in error, and further identify said collection of input signals to be
(i) input signals of the circuit, or
(ii) internal signals of said circuit Sj,i(k), with index l incremented by 1, that are output signal of memory elements of said circuit, each storing associated p logic values, and each having been subjected to an input signal Sj,i(m−p);
(d) setting m to m−p, thus forming signals Sj,i(m), and with respect to each of the formed signals Sj,l(m) returning to step (a);
and
(e) terminating said method when no input signals of any fanin code is identified as an output signal of a memory element of said circuit.

8 more elements

Dependencies are inferred from the claim text.