G01R 31/318552
Clock circuits details
Official title: {Clock circuits details}
G01R31/318552 (Clock circuits details) appears on 602 US grants and 504 published applications in this corpus.
Search patents in G01R- Granted patents
- 602
- Published applications
- 504
- Assignees
- 172
- Inventors
- 981
- Latest grant
- 6 Oct 2026
Filings by year
| Year | Granted patents | Published applications |
|---|---|---|
| 1988 | 3 | 0 |
| 1989 | 2 | 0 |
| 1990 | 3 | 0 |
| 1991 | 4 | 0 |
| 1992 | 2 | 0 |
| 1993 | 8 | 0 |
| 1994 | 6 | 0 |
| 1995 | 4 | 0 |
| 1996 | 9 | 0 |
| 1997 | 13 | 0 |
| 1998 | 11 | 0 |
| 1999 | 8 | 0 |
| 2000 | 7 | 0 |
| 2001 | 14 | 6 |
| 2002 | 14 | 26 |
| 2003 | 20 | 22 |
| 2004 | 23 | 26 |
| 2005 | 23 | 30 |
| 2006 | 19 | 15 |
| 2007 | 24 | 26 |
| 2008 | 23 | 19 |
| 2009 | 24 | 21 |
| 2010 | 26 | 25 |
| 2011 | 23 | 17 |
| 2012 | 15 | 14 |
| 2013 | 23 | 14 |
| 2014 | 22 | 23 |
| 2015 | 18 | 25 |
| 2016 | 28 | 20 |
| 2017 | 18 | 12 |
| 2018 | 15 | 16 |
| 2019 | 23 | 15 |
| 2020 | 15 | 17 |
| 2021 | 14 | 16 |
| 2022 | 15 | 10 |
| 2023 | 29 | 23 |
| 2024 | 17 | 26 |
| 2025 | 24 | 25 |
| 2026 | 13 | 15 |
By publication year. Applications have been published since 2001. 2026 runs to 8 Oct.
Recent patents
- Data correction and phase optimization in high-speed receivers6 Oct 2026US 12,754,237 B2Diodes Incorporated
- High performance data latching using an energy efficient clocked latch topology15 Sep 2026US 12,738,929 B2International Business Machines Corporation
- System and method for controlling at-speed testing of integrated circuits25 Aug 2026US 12,716,942 B2NXP B. V.
- Integrated-circuit chip for retention cell testing23 Jun 2026US 12,663,469 B2Nordic Semiconductor ASA
- Integrated circuit with multiplexer for testing16 Jun 2026US 12,656,397 B2Samsung Electronics Co., Ltd.
- System for Directional Scan Access and Method for Directional Scan Testing Thereof24 Sep 2026US 2026/0287656 A1
- Efficient scannable register file cell with low overhead3 Sep 2026US 2026/0259262 A1International Business Machines Corporation
- Scan test in a single-wire bus circuit3 Sep 2026US 2026/0259263 A1Qorvo US, Inc.
- Clock gating based on care bits in scan chains for reduced clock power during scan automatic test pattern generation13 Aug 2026US 2026/0235674 A1
- Circuitry for Staggering Capture Clocks in Testing Electronic Circuits with Multiple Clock Domains6 Aug 2026US 2026/0227442 A1Synopsys, Inc.
Most cited
By later US patents
- Apparatus for at-speed testing, in inter-domain mode, of a multi-clock-domain digital integrated circuit according to BIST or SCAN techniques226US 8,862,955 B2STMicroelectronics S,r.l. · 2014
- Low cost emulation scheme implemented via clock control using JTAG controller in a scan environment174US 5,812,562 ASamsung Electronics Co., Ltd. · 1998
- Multiple clock rate test apparatus for testing digital systems134US 5,349,587 ANorthern Telecom Limited · 1994
- Efficient fir filter for high-speed communication118US 6,272,173 B1Broadcom Corporation · 2001
- Method and apparatus for testing circuits with multiple clocks117US 6,442,722 B1LogicVision, Inc. · 2002