Multiple clock rate test apparatus for testing digital systems

A method for testing a digital system comprising a plurality of scannable memory elements and at least one combinational network, the method comprising:

• configuring the memory elements in a scan mode in which the memory elements are connected to define a plurality of scan chains;
• clocking a test stimulus pattern into each of the scan chains at a respective clock rate during a respective scan-in interval, at least two of the clock rates being different from one another, all respective scan-in intervals overlapping in tome for a plurality of clock cycles at a highest of the respective clock rates;
• configuring the memory elements of each scan chain in a normal operation mode during a respective normal mode interval, the memory elements of each scan chain being interconnected by the combinational network in the normal operation mode, all respective normal mode intervals overlapping in time for at least one clock cycle at the highest of the respective clock rates;
• configuring the memory elements in the scan mode;
• and
• clocking a test response pattern out of each of the scan chains at its respective clock rate during a respective scan-out interval, all respective scan-out intervals overlapping in time for a plurality of clock cycles at the highest of the respective clock rates.

A digital system comprising:

• at least one combinational network;
• a plurality of scannable memory elements, the memory elements being configurable in a normal operation mode in which the memory elements are interconnected by the combinational network and being configurable in a scan mode in which the memory elements are connected to define a plurality of scan chains;
• a multiple clock generator for generating multiple clock signals for clocking test patterns into and out of each of the scan chains at a respective clock rate, at least tow of the clock rates being different from one another;
• and
• a configuration controller for configuring the memory elements in scan mode to permit clocking of test stimulus patterns into each scan chain at its respective clock rate, for reconfiguring the memory elements in normal operation mode for at least one clock cycle at a highest of the respective clock rates, and for reconfiguring the memory elements in scan mode to permit clocking of test response patterns out of each scan chain at its respective clock rate.