Circuitry for Staggering Capture Clocks in Testing Electronic Circuits with Multiple Clock Domains

Abstract

In some aspects, an integrated circuit includes a plurality of clock domains. Each clock domain includes functional circuitry and an on-chip clock controller. The functional circuitry includes scan flip-flops that are connected into one or more scan chains that cross clock domains. The on-chip controllers generate capture pulses that used for scan tests. To run scan tests, test patterns are loaded into the scan chains during scan-in phases clocked by a scan clock, the functional circuitry is operated in response to the test patterns and is clocked by sequences of capture pulses generated by the on-chip clock controllers, and test responses produced by the operation of the functional circuitry are read out from the scan chains during scan-out phases clocked by the scan clock. The on-chip clock controllers generate the capture pulses delayed by stagger periods. The stagger periods are adjustable and are based on the scan clock.

Dependencies are inferred from the claim text.