Method and apparatus for testing circuits with multiple clocks

A method of testing a circuit having two or more clock domains at respective domain test clock rates and under control of a main test clock signal, said circuit having core logic, a plurality of scannable memory elements, each having a clock input, an input connected to an output of said core logic and/or an output connected to an input to said core logic, and configurable in scan mode in which said memory elements are connected to define one or more scan chains in each said domain and in normal mode in which said memory elements are connected to said core logic in normal operational mode, said method comprising:

• configuring said memory elements in scan mode including:
• for each synchronous domain in which respective domain test clock signal is synchronous with respect to said main test clock signal, generating and applying active memory element configuration signals to memory elements in said synchronous domains;
• for each asynchronous clock domain in which the domain test clock signal thereof is asynchronous with respect to said main test clock signal, generating an active configuration control signal, generating active memory element scan mode configuration signals and applying said memory element configuration signals to said memory elements;
• and
• concurrently clocking a test stimulus into each scan chain of each said clock domain including:
• for each synchronous clock domain, clocking said test stimulus at a domain shift clock rate derived from said main test clock signal and,
• for each asynchronous clock domain:
• generating respective first and second domain shift clock signals, said first domain shift clock signal being derived from said main test clock signal and said second domain shift clock signal being derived from said respective domain test clock signal;
• selecting said first domain shift clock signal as a domain clock signal;
• clocking all but a predetermined number of bits of said test stimulus under control of said domain clock signal;
• generating an inactive configuration control signal,
• suppressing said domain clock signal for a predetermined time interval in response to said inactive configuration control signal;
• selecting said second domain shift clock signal as said domain clock signal;
• activating said domain clock signal and clocking said predetermined number of bits of said test stimulus at under control of said domain clock signal;
• configuring said memory elements of each scan chain in normal mode during an overlapping normal mode interval in which the memory elements of each scan chain are interconnected by said core logic in the normal operational mode, all respective normal mode intervals overlapping in time such that a value captured by said memory elements is a combinational function of test data shifted into said memory elements;
• configuring said memory elements in scan mode including:
• for each asynchronous clock domain, generating an active configuration control signal, generating active memory element scan mode configuration signals and applying said memory element configuration signals to said memory elements, and
• for each synchronous domain, generating and applying active memory element configuration signals to memory elements in said synchronous domains;
• clocking each memory element in each scan chain at its respective domain test clock rate for at least one clock cycle thereof;
• clocking a test response pattern out of each of the scan chains including:
• for each asynchronous clock domain, clocking said test response pattern under the control of said first domain shift clock signal;
• and
• for each synchronous clock domain, clocking a test response pattern therefrom under control of its respective domain shift clock signal;
• and
• analyzing said test response pattern from each said clock domain.

A test controller for use in testing an integrated circuit having core logic circuitry and two or more clock domains operable at respective domain clock rates, each clock domain having a plurality of scannable memory elements, each having a clock input, an input connected to an output of said core logic and/or an output connected to an input to said core logic, and configurable in scan mode in which said memory elements are connected to define one or more scan chains in each said domain and in normal mode in which said memory elements are connected to said core logic in normal operational mode, said test controller comprising:

• a primary test controller for controlling circuit test operations under control of a main test clock signal, said primary test controller being operable to:
• concurrently load a test stimulus to each scan chain in each clock domain and receive response data from each said scan chain at respective domain shift clock rates;
• generate respective domain shift clock signals derived from said main test clock signal for each clock domain;
• generate a mode control signal for each synchronous clock domain;
• and
• generate respective domain configuration control signal for each asynchronous clock domain in which the domain test clock signal is asynchronous with respect to said main test clock signal;
• and
• an auxiliary test controller associated with each said asynchronous clock domain for controlling test operations therein under control of said primary test controller, each said auxiliary test controller being operable to generate a memory element clock signal derived from said respective domain shift clock signal when said respective domain configuration control signal is active and derived from said domain test clock signal when said domain configuration control signal is inactive;
• each said auxiliary test controller being responsive to said respective configuration control signal by generating memory element configuration signals operable for configuring said memory elements in said scan mode or said normal mode.

A test controller for use in testing an integrated circuit having core logic circuitry and two or more clock domains operable at respective domain clock rates, each clock domain having a plurality of scannable memory elements, each having a clock input, an input connected to an output of said core logic and/or an output connected to an input to said core logic, and configurable in scan mode in which said memory elements are connected to define one or more scan chains in each said domain and in normal mode in which said memory elements are connected to said core logic in normal operational mode, said test controller comprising:

• a primary test controller for controlling circuit test operations under control of a main test clock signal, said primary test controller including:
• a pseudo random pattern generator operable under control of said main test clock signal for concurrently generating a test stimulus for each scan chain in each clock domain;
• a multiple input signature analyser operable under control of said main test clock signal for receiving and analysing response data from each said scan chain;
• a circuit for generating a domain shift clock signal derived from said main test clock signal for each clock domain;
• and
• a circuit for generating a configuration control signal for each said clock domain;
• and
• an auxiliary test controller associated with each asynchronous clock domain for controlling test operations therein, each said auxiliary test controller receiving a respective domain shift clock signal from said primary controller and a respective domain test clock signal;
• each said auxiliary test controller including:
• means responsive to said configuration control signal for generating memory element configuration signals for configuring said memory elements in a scan mode or normal mode;
• a clock signal generating circuit for generating and applying a local clock signal to the clock input of said memory elements, said clock signal generating circuit including:
• a shift clock generating circuit responsive to said configuration control signal and said respective domain shift clock signal and producing a shift clock signal corresponding to said respective domain shift clock signal;
• and
• a capture clock signal generating circuit responsive to said configuration control signal and said predetermined domain clock signal for producing a capture clock signal corresponding to said respective domain test clock signal;
• and
• means receiving said shift clock signal and said capture clock and selectively outputting one of said shift and capture clock signals as said local clock signal.

In a test controller for testing an integrated circuit having core logic circuitry and two or more clock domains operable at respective domain clock rates, each clock domain having a plurality of scannable memory elements, each having a clock input, an input connected to an output of said core logic and/or an output connected to an input to said core logic, and configurable in scan mode in which said memory elements are connected to define one or more scan chains in each said domain and in normal mode in which said memory elements are connected to said core logic in normal operational mode, the improvement comprising:

• a primary controller for controlling circuit test operations under control of a main test clock signal and for controlling testing of synchronous clock domains whose domain test clock signal is synchronous with respect to said main test clock signal, said primary controller generating a respective shift clock signal derived from said main test clock signal for each clock domain, and a configuration control signal for each asynchronous clock domain in said circuit;
• and
• an auxiliary controller associated with each asynchronous clock domain whose domain test clock signal is not synchronous with respect to said main test clock signal, and each said auxiliary controller being responsive to said primary controller for controlling testing of its associated clock domain, each auxiliary controller generating a memory element clock signal and responsive to an active configuration clock signal for applying its respective domain shift clock signal to said memory elements and responsive to an inactive configuration control signal for applying said domain test clock signal to said memory elements.