Integrated-circuit chip for retention cell testing
AssigneeNordic Semiconductor ASA
InventorAshraf Mohammed
Life of this patent
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Abstract
An integrated-circuit chip comprises a plurality of scan flip-flops and a retention cell. The chip is configured to have a scan-capture mode, in which the plurality of scan flip-flops and the retention cell are connected to respective functional circuitry of the integrated-circuit chip, and to have a scan-shift mode, in which the plurality of scan flip-flops and the retention cell are connected so as to form a scan chain for use during scan-chain testing of the integrated-circuit chip. The chip further comprises on-chip test circuitry arranged to generate and output a save signal, a clock signal, and a restore signal to the retention cell, for testing the retention cell during scan-chain testing of the integrated-circuit chip.
Claims20
An integrated-circuit chip comprising:
- a plurality of scan flip-flops;
- and
- a retention cell;
- wherein the integrated-circuit chip is configured to have a scan-capture mode, in which the plurality of scan flip-flops and the retention cell are connected to respective functional circuitry of the integrated-circuit chip, and to have a scan-shift mode, in which the plurality of scan flip-flops and the retention cell are connected so as to form a scan chain for use during scan-chain testing of the integrated-circuit chip;
- and
- wherein the integrated-circuit chip further comprises on-chip test circuitry arranged to generate and output a save signal, a clock signal, and a restore signal to the retention cell, for testing the retention cell during scan-chain testing of the integrated-circuit chip.
A method of operating an integrated-circuit chip, wherein the integrated-circuit chip comprises:
- a plurality of scan flip-flops;
- a retention cell;
- and
- on-chip test circuitry configured to generate and output save, clock and restore signals to the retention cell,
- the method comprising, during a scan-chain testing of the integrated-circuit chip:
- operating the integrated-circuit chip in a scan-shift mode, in which the plurality of scan flip-flops and the retention cell are connected so as to form a scan chain;
- operating the integrated-circuit chip in a scan-capture mode, in which the plurality of scan flip-flops and the retention cell are connected to respective functional circuitry of the integrated-circuit chip;
- and
- using the on-chip test circuitry to generate and output a save signal, a clock signal and a restore signal to the retention cell.
Dependencies are inferred from the claim text.