Efficient scannable register file cell with low overhead

A scannable register comprising:

• a plurality of scannable memory cells arranged in an array, each of the plurality of scannable memory cells comprising:
• a first inverter and a second inverter cross-coupled with the first inverter;
• a first scan access transistor coupled to the first and second inverters;
• and
• a second scan access transistor coupled to the first and second inverters, wherein:
• for a first scannable memory cell of the plurality of scannable memory cells, the first and second scan access transistors of the first scannable memory cell are clocked by a first test clock signal;
• and
• for a second scannable memory cell of the plurality of scannable memory cells adjacent to the first scannable memory cell:
• the first and second scan access transistors of the second scannable memory cell are clocked by a second test clock signal different from the first test clock signal;
• and
• the first and second scan access transistors of the second scannable memory cell are coupled to the first and second inverters of the first scannable memory cell;
• and
• a latch coupled to the second scannable memory cell.

A method for performing a scan test of an integrated circuit, the method comprising:

• loading first test scan content into a first scannable memory cell of a scan chain comprising a plurality of scannable memory cells arranged in an array;
• and
• performing a scan test on the scan chain, comprising controlling, via a first test clock signal, the first scannable memory cell to overwrite content of a second scannable memory cell of the scan chain with the first test scan content, wherein:
• the first scannable memory cell is adjacent to the second scannable memory cell within the scan chain;
• the second scannable memory cell is clocked by the first test clock signal;
• and
• the first scannable memory cell is clocked by a second test clock signal different from the first test clock signal.