System and method for controlling at-speed testing of integrated circuits

An integrated circuit (IC), comprising:

• a clocking system configured to receive a reference clock signal and generate an at-speed clock signal, wherein during a capture phase of an at-speed testing of the IC, the at-speed clock signal comprises a launch pulse and a capture pulse that are extracted from the reference clock signal based on a frequency associated with the capture phase;
• a plurality of clock gate controllers configured to generate a plurality of enable signals such that for the launch pulse, one of the plurality of enable signals is asserted, and for the capture pulse, one of a group consisting of (i) the same enable signal and (ii) a different enable signal, of the plurality of enable signals, is asserted;
• and
• a plurality of clock gates that is coupled to the plurality of clock gate controllers, and configured to receive the plurality of enable signals, wherein each clock gate of the plurality of clock gates is activated based on an assertion of a corresponding enable signal, and wherein during the capture phase, (i) each of the plurality of clock gates is further configured to receive the at-speed clock signal and (ii) one or more activated clock gates, of the plurality of clock gates, are configured to enable the at-speed testing of the IC based on the at-speed clock signal;
• wherein the clocking system comprises a test controller that is configured to generate a plurality of domain trigger signals and provide the plurality of domain trigger signals to the plurality of clock gate controllers, wherein during the capture phase, each domain trigger signal is asserted based on a data launch operation and a data capture operation of the capture phase being executed in a clock domain associated with the corresponding clock gate controller, and wherein the plurality of enable signals is same as the plurality of domain trigger signals during the capture phase.

A method for controlling an at-speed testing of an integrated circuit (IC), the method comprising:

• receiving, by a clocking system, a reference clock signal;
• generating, by the clocking system, an at-speed clock signal such that during a capture phase of the at-speed testing, the at-speed clock signal comprises a launch pulse and a capture pulse that are extracted from the reference clock signal based on a frequency associated with the capture phase;
• generating, by a plurality of clock gate controllers, a plurality of enable signals such that for the launch pulse, one of the plurality of enable signals is asserted, and for the capture pulse, one of a group consisting of (i) the same enable signal and (ii) a different enable signal, of the plurality of enable signals, is asserted;
• receiving, by a plurality of clock gates, the plurality of enable signals from the plurality of clock gate controllers, wherein each of the plurality of clock gates is activated based on an assertion of a corresponding enable signal;
• receiving, by each of the plurality of clock gates, the at-speed clock signal during the capture phase;
• and
• enabling, during the capture phase, by one or more activated clock gates of the plurality of clock gates, the at-speed testing of the IC based on the at-speed clock signal;
• wherein the clocking system comprises:
• a launch shift register and a capture shift register, each configured to receive the reference clock signal;
• and
• a register control circuit that is coupled to the launch shift register and the capture shift register, and configured to determine a launch configuration value and a capture configuration value based on the frequency associated with the capture phase and load the launch configuration value and the capture configuration value in the launch shift register and the capture shift register, respectively,
• wherein the launch configuration value comprises a first plurality of data bits that is shifted in the launch shift register based on the reference clock signal such that for each cycle of the reference clock signal, the launch shift register is further configured to output a data bit of the launch configuration value as a launch pulse data bit,
• wherein the capture configuration value comprises a second plurality of data bits that is shifted in the capture shift register based on the reference clock signal such that for each cycle of the reference clock signal, the capture shift register is further configured to output a data bit of the capture configuration value as a capture pulse data bit, and
• wherein the launch pulse data bit and the capture pulse data bit enable the extraction of the launch pulse and the capture pulse from the reference clock signal, respectively.