Integrated circuit with multiplexer for testing

An integrated circuit comprising:

• a plurality of combinational logic circuits comprising:
• a first combinational logic circuit configured to generate a first output signal, and
• a second combinational logic circuit configured to generate a second output signal and output the second output signal to a primary output terminal;
• a plurality of flip-flops comprising a first flip-flop configured to receive a first scan input signal and a first data signal;
• and
• a first core block comprising a multiplexer, the multiplexer being configured to select, based on a test control signal, at least one of the first output signal received from the first combinational logic circuit or the second output signal received from the second combinational logic circuit and provide the selected signal as the first data signal to the first flip-flop,
• wherein the first flip-flop is configured to selectively receive, based on a scan control signal, at least one of the first scan input signal or the first data signal.

An integrated circuit comprising:

• a plurality of combinational logic circuits comprising a first combinational logic circuit and a second combinational logic circuit;
• a plurality of flip-flops comprising a first flip-flop configured to receive a first scan input signal and a first data signal;
• a first multiplexer configured to select, based on a first test control signal, at least one of a first primary input signal received through a first primary input terminal or an output signal of the first flip-flop and output the selected signal as a first selection signal;
• and
• a first core block comprising a second multiplexer, the second multiplexer being configured to receive the first selection signal from the first multiplexer, and select, based on a second test control signal, at least one of a second primary input signal received through a second primary input terminal or the first selection signal, and provide the selected signal as a second selection signal to the first combinational logic circuit,
• wherein the first flip-flop is configured to selectively receive, based on a scan control signal, at least one of the first scan input signal or the first data signal.