G01R 31/318569
Error indication, logging circuits
Official title: {Error indication, logging circuits}
G01R31/318569 (Error indication, logging circuits) appears on 89 US grants and 83 published applications in this corpus.
Search patents in G01R- Granted patents
- 89
- Published applications
- 83
- Assignees
- 58
- Inventors
- 182
- Latest grant
- 6 Oct 2026
Filings by year
| Year | Granted patents | Published applications |
|---|---|---|
| 1982 | 1 | 0 |
| 1983 | 0 | 0 |
| 1984 | 0 | 0 |
| 1985 | 0 | 0 |
| 1986 | 0 | 0 |
| 1987 | 0 | 0 |
| 1988 | 0 | 0 |
| 1989 | 1 | 0 |
| 1990 | 1 | 0 |
| 1991 | 1 | 0 |
| 1992 | 0 | 0 |
| 1993 | 0 | 0 |
| 1994 | 2 | 0 |
| 1995 | 2 | 0 |
| 1996 | 0 | 0 |
| 1997 | 0 | 0 |
| 1998 | 1 | 0 |
| 1999 | 1 | 0 |
| 2000 | 1 | 0 |
| 2001 | 1 | 1 |
| 2002 | 2 | 0 |
| 2003 | 1 | 4 |
| 2004 | 3 | 6 |
| 2005 | 2 | 4 |
| 2006 | 7 | 6 |
| 2007 | 3 | 3 |
| 2008 | 2 | 10 |
| 2009 | 5 | 0 |
| 2010 | 4 | 2 |
| 2011 | 4 | 3 |
| 2012 | 3 | 1 |
| 2013 | 4 | 6 |
| 2014 | 2 | 4 |
| 2015 | 5 | 1 |
| 2016 | 1 | 4 |
| 2017 | 1 | 3 |
| 2018 | 4 | 2 |
| 2019 | 5 | 2 |
| 2020 | 3 | 2 |
| 2021 | 2 | 4 |
| 2022 | 3 | 4 |
| 2023 | 5 | 6 |
| 2024 | 3 | 0 |
| 2025 | 2 | 1 |
| 2026 | 1 | 4 |
By publication year. Applications have been published since 2001. 2026 runs to 8 Oct.
Recent patents
- I3C error states test strategy6 Oct 2026US 12,754,235 B2Microchip Technology Incorporated
- Circuits and methods for configurable scan chains9 Sep 2025US 12,411,174 B2Altera Corporation
- Managing data protection settings for an electronic control unit19 Aug 2025US 12,394,257 B2Rivian IP Holdings, LLC
- Method and system for testing an integrated circuit11 Jun 2024US 12,007,438 B2Taiwan Semiconductor Manufacturing Company.Ltd
- Boundary scan test method and storage medium19 Mar 2024US 11,933,845 B2Shenzhen Pango Microsystems Co., Ltd
- Multi-phase synchronized method for lane margining1 Oct 2026US 2026/0299021 A1SK hynix Inc.
- Semiconductor device and method of inspecting semiconductor device13 Aug 2026US 2026/0235675 A1Canon Kabushiki Kaisha
- I3c error states test strategy30 Apr 2026US 2026/0118421 A1Microchip Technology Incorporated
- Electronic device and operation method therefor23 Apr 2026US 2026/0110734 A1LG Electronics Inc.
- Monitor block, interface circuit, and method of operating debugging system31 Jul 2025US 2025/0244385 A1Samsung Electronics Co., Ltd.
Most cited
By later US patents
- Method and apparatus for testing digital systems46US 4,945,536 ANorthern Telecom Limited · 1990
- JTAG instruction error detection42US 5,377,198 ANCR Corporation (nka AT&T Global Information Solutions Company · 1994
- Fault capture/fault injection system40US 4,996,688 AUnisys Corporation · 1991
- Diagnostic method for structural scan chain designs39US 6,961,886 B2International Business Machines Corporation · 2005
- Device for testing digital circuits using built-in logic block observers (BILBO's)31US 4,340,857 ASiemens Aktiengesellschaft · 1982