US 5,377,198 AGranted

JTAG instruction error detection

AssigneeNCR Corporation (nka AT&T Global Information Solutions Company

InventorsDavid L. Simpson, Mark A. Taylor

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Abstract

A method for detecting JTAG errors in which components in a boundary scan path of a JTAG serial test bus connect a single bit bypass register into the scan path rather than the expected register when errors are detected. JTAG instruction signals are shifted into the scan path to determine whether an instruction error was received by a component. Data scanned into the component is prefixed by a header which is monitored by the JTAG control circuitry to detect any instruction errors. The combined data and header are padded by bits preceding the header to be equal to a multiple of a data register contained within the JTAG control circuitry. The least significant bit positions of the header and the padding bits are shifted out of the data register prior to the time that the header or first byte of the header should have been in the data register of the JTAG control circuitry such that the least significant bit of the data register is a 1, if no single error occurred, and is a 0 if a single error occurred.

Claims8

Dependent claims

A method for detecting errors in instructions used to control a serial test bus in a computer system, said serial test bus operating with a plurality of system components each having an instruction register, a bypass register and a boundary scan register selectively connectable into a serial bus path, said method comprising the steps of:

setting up said plurality of components to connect instruction registers to receive instructions to be performed within said components via said serial bus path;
shifting instructions to be performed within said components into said instruction registers;
checking the validity of said instructions shifted into said instruction registers;
setting up all of said plurality of components having instruction registers containing valid instructions to connect their boundary scan registers to receive data corresponding to said valid instructions via said serial bus path;
setting up all of said plurality of components having instruction registers containing invalid instructions to connect their bypass registers to said serial bus path;
prefixing data to be shifted into said boundary scan registers with a header having a length equal to the length of the longest boundary scan register in said serial bus path and having a predetermined number of least significant bits equal to the same digital value, wherein the predetermined number is a function of the length of the shortest boundary scan register in said serial bus path;
shifting said data and header into said components;
receiving signals shifted out of said components as said data and header are shifted into said components;
and
monitoring a portion of said signals shifted out of said components which should correspond to said header to detect errors in said instructions used to control said serial test bus.

7 more elements

Dependencies are inferred from the claim text.