Boundary scan test method and storage medium
AssigneeShenzhen Pango Microsystems Co., Ltd
InventorsShiyjun Zhao, Puxia Liu, Qipan Fu
Life of this patent
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Abstract
A boundary scan test method is used to test connectivity of a pad having a direct connection to user logic. The method comprises the following steps: configuring an FPGA to enter a test mode; generating by means of user logic, a boundary scan chain for a boundary scan test; loading a boundary scan test instruction to the FPGA, and loading a PRELOAD instruction to a device having a pad to be tested for connectivity; sending, via a TDI port, a first test vector to the pad; performing the boundary scan test, and loading an EXTEST instruction to the device having the pad; and removing first response data from a TDO port, and performing response analysis and fault diagnosis.
Claims16
A boundary scan test method for testing the connectivity of a PAD having a direct connection to user logic comprising the following steps:
- configuring an FPGA to enter a test mode;
- configuring a boundary scan chain for a boundary scan test by means of the user logic;
- loading a boundary scan test instruction to the FPGA, and loading a PRELOAD instruction to a device having a PAD to be tested for connectivity;
- sending, a first test vector to the PAD via a TDI port;
- performing the boundary scan test, and loading an EXTEST instruction to the device having the PAD;
- and
- removing first response data from a TDO port and performing response analysis and fault diagnosis:
- wherein the step “configuring a boundary scan chain for a boundary scan test by means of the user logic” further comprises:
- according to a position and a quantity of PADs to be tested, configuring a boundary scan chain corresponding to the PADs to be tested one by one through the user logic:
- the PAD is controlled to be an input state or an output state by the control unit, for the input PAD, in the CAPTURE-DR state, the input value is captured to the data unit, and in the UPDATE-DR state, the value of the shift register in the control unit is updated to the second stage register;
- for the output PAD, in the UPDATE-DR state, update the value of the shift register in the data unit and the control unit to the second-level register.
A non-transitory storage medium storing at least one program instruction, wherein a method is implemented when the program instruction is executed by a processor;
- and wherein the method comprises the following steps:
- configuring an FPGA to enter a test mode;
- configuring a boundary scan chain for a boundary scan test by means of the user logic;
- loading a boundary scan test instruction to the FPGA, and loading a PRELOAD instruction to a device having a PAD to be tested for connectivity;
- sending, a first test vector to the PAD via a TDI port;
- performing the boundary scan test, and loading an EXTEST instruction to the device having the PAD;
- and
- removing first response data from a TDO port and performing response analysis and fault diagnosis;
- wherein the step “configuring a boundary scan chain for a boundary scan test by means of the user logic” further comprises:
- according to a position and a quantity of PADs to be tested, configuring a boundary scan chain corresponding to the PADs to be tested one by one through the user logic.
Dependencies are inferred from the claim text.