Method and apparatus for testing digital systems

A method for testing a digital system having a plurality of system terminals for coupling input signals into the system and output signals out of the system during normal operation of the system, the method comprising:

• connecting at least some of the system terminals in parallel to boundary register means, said boundary register means being operable to generate input signals and to pass said input signals from the boundary register means to selected system terminals while receiving output signals from selected system terminals and concurrently accumulating together said input signals and said output signals;
• initializing the state of the digital system and the state of the boundary register means to predetermined states;
• running the digital system and boundary register means through a predetermined number of clock cycles to generate input signals and to pass said input signals from the boundary register means to selected system terminals while receiving output signals from selected system terminals and accumulating together within the boundary register means said input signals and output signals to generate a test result pattern;
• and
• comparing the generated test result pattern to a predetermined test result pattern.

Test apparatus for testing a digital system having a plurality of system terminals for coupling input signals into the system and output signals out of the system during normal operation of the system, the test apparatus comprising:

• boundary register means for connection in parallel to at least some of the system terminals, said boundary register means being operable to pass input signals and output signals transparently through the boundary register means while accumulating together said input signals and output signals;
• means for initializing the state of the digital system and the state of the boundary register means to predetermined states;
• means for running the digital system through a predetermined number of clock cycles while passing known input signals through the boundary register means into the system and accumulating together within the boundary register means said known input signals and output signals provided by the digital system to generate a test result pattern;
• and
• means for comparing the generated test result pattern to a predetermined test result pattern.

Test apparatus for testing a digital system having a plurality of system terminals for coupling input signals into the system and output signals out of the system during normal operation of the system, the test apparatus comprising:

• boundary register means for connection in parallel to at least some of the system terminals, said boundary register means being operable to generate input signals and to pass said input signals from the boundary register means to selected system terminals while receiving output signals from selected system terminals and accumulating together said input signals and said output signals;
• means for initializing the state of the digital system and the state of the boundary register means to predetermined states;
• means for running the digital system through a predetermined number of clock cycles generate input signals and to pass said input signals from the boundary register means to selected system terminals while receiving output signals from the selected system terminals and accumulating together within the boundary register means said input signals and output signals to generate a test result pattern;
• and
• means for comparing the generated test result pattern to a predetermined test result pattern.

A digital integrated circuit, comprising:

• a digital system having a plurality of system terminals for coupling input signals into the system and output signals out of the system during normal operation of the system;
• a plurality of integrated circuit terminals for coupling input signals into the integrated circuit and output signals out of the integrated circuit;
• and
• boundary register means connected in parallel between corresponding integrated circuit terminals and system terminals, said boundary register means being operable to pass input signals and output signals transparently through the boundary register means while accumulating together said input signals and output signals.

A boundary register cell, comprising:

• a serial input terminal;
• a serial output terminal;
• a parallel input terminal;
• a parallel output terminal;
• control terminal means;
• and
• signal gating and accumulation means operably connected to the serial input terminal, the serial output terminal, the parallel input terminal, the parallel output terminal and the control terminal means, the signal gating and accumulation means being:
• responsive to a first predetermined signal on the control terminal means to transfer a serial input bit from the serial input terminal to the serial output terminal;
• responsive to a second predetermined control signal on the control terminal means to transfer a parallel input bit from the parallel input terminal to the parallel output terminal;
• and
• responsive to a third predetermined signal on the control terminal means to transfer a parallel input bit from the parallel input terminal to the parallel output terminal and to transfer a serial output bit to the serial output terminal, the serial output bit comprising the modulo 2 sum of the parallel input bit applied to the parallel input terminal and a serial input bit applied to the serial input terminal, the third predetermined signal being different from the first and second predetermined signals.

A boundary register cell, comprising:

• a serial input terminal;
• a serial output terminal;
• a first parallel input/output terminal;
• a second parallel input/output terminal;
• control terminal means;
• and
• signal gating and accumulation means operably connected to the serial input terminal, the serial output terminal, the first parallel input/output terminal, the second parallel input/output terminal and the control terminal means, the signal gating and compression means being:
• responsive to a first predetermined signal on the control terminal means to transfer a serial input bit from the serial input terminal to the serial output terminal;
• responsive to a second predetermined control signal on the control terminal means to transfer a parallel input bit from the first parallel input/output terminal to the second parallel input/output terminal;
• responsive to a third predetermined signal on the control terminal means to transfer a parallel input bit from the first parallel input/output terminal to the second parallel input/output terminal and to apply a serial output bit to the serial output terminal, the serial output bit comprising the modulo 2 sum of the parallel input bit applied to the first parallel input/output terminal and a serial input bit applied to the serial input terminal, the third predetermined signal being different from the first and second predetermined signals;
• responsive to a fourth predetermined control signal on the control terminal means to transfer a parallel input bit from the second parallel input/output terminal to the first parallel input/output terminal, the fourth predetermined signal being different from the second and third predetermined signals;
• and
• responsive to a fifth predetermined signal on the control terminal means to transfer a parallel input bit from the second parallel input/output terminal to the first parallel input/output terminal and to transfer a serial output bit to the serial output terminal, the serial output bit comprising the modulo 2 sum of the parallel input bit applied to the second parallel input/output terminal and a serial input bit applied to the serial input terminal, the fifth predetermined signal being different from the first, second, third and fourth predetermined signals.