Method and system for testing an integrated circuit
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsChi-Che Wu, Tsung-Yang Hung, Ming-Yih Wang
Life of this patent
Estimating the term…
Abstract
A method is provided and includes several operations: testing multiple scan chains in multiple shift cycles to obtain multiple values; determining at least one fail chain in the scan chains and determining at least one fail shift cycle corresponding to at least one fail value in the values; mapping the at least one fail chain and the at least one fail shift cycle to the scan chains to identify the at least one fail flip flop; and identifying at least one fault site corresponding to the at least one fail flip flop.
Claims20
A method, comprising:
- testing a plurality of scan chains in a plurality of shift cycles to obtain a plurality of values;
- determining at least one fail chain in the plurality of scan chains and determining at least one fail shift cycle corresponding to at least one fail value in the plurality of values;
- generating a mapping table, including the plurality of shift cycles, the plurality of values, and a plurality of pins outputting the plurality of values;
- mapping, through the mapping table, the at least one fail chain and the at least one fail shift cycle to the plurality of scan chains to identify an at least one fail flip flop;
- and
- identifying at least one fault site corresponding to the at least one fail flip flop.
A method, comprising:
- loading a plurality of values into a first scan chain at a first voltage level and storing the plurality of values in the first scan chain;
- operating the first scan chain at a second voltage level different from the first voltage level;
- clocking the plurality of values out as a plurality of outputted values in a plurality of shift cycles at the first voltage level;
- comparing the plurality of outputted values with the plurality of values to generate a fail log;
- and
- determining, based on the fail log and a mapping table, whether a fail flip flop is in the first scan chain.
A system, comprising:
- one or more processing units;
- and
- a storage unit configured to store instructions that when executed by at least one of the one or more processing units perform operations, comprising:
- generate a test pattern based on a scan chain pattern to a tester to operate an integrated circuit swinging between a first voltage level and a second voltage level lower than the first voltage level to generate a resultant pattern;
- detect at least one fail resultant value in the resultant pattern from the tester;
- determine at least one fail shift cycle corresponding to the at least one fail resultant value;
- and
- determine, based on a mapping table, at least one fail flip flop associated with the at least one fail shift cycle.
Dependencies are inferred from the claim text.