Synopsys, Inc.
Sunnyvale, CA, US· latest recorded location
Synopsys, Inc. is named on 2,589 US grants and 1,902 published applications in this corpus. Its most frequent classification is G06F (Computing and data processing).
- Granted patents
- 2,589
- Published applications
- 1,902
- Inventors
- 2,663
- Granted in 2026 so far
- 102
- Most recent grant
- 29 Sep 2026
Filings by year
| Year | Granted patents | Published applications |
|---|---|---|
| 1994 | 3 | 0 |
| 1995 | 0 | 0 |
| 1996 | 4 | 0 |
| 1997 | 12 | 0 |
| 1998 | 19 | 0 |
| 1999 | 21 | 0 |
| 2000 | 25 | 0 |
| 2001 | 24 | 0 |
| 2002 | 29 | 11 |
| 2003 | 19 | 13 |
| 2004 | 20 | 26 |
| 2005 | 42 | 33 |
| 2006 | 45 | 60 |
| 2007 | 73 | 79 |
| 2008 | 58 | 81 |
| 2009 | 77 | 90 |
| 2010 | 85 | 110 |
| 2011 | 140 | 126 |
| 2012 | 141 | 81 |
| 2013 | 176 | 122 |
| 2014 | 200 | 142 |
| 2015 | 119 | 120 |
| 2016 | 106 | 98 |
| 2017 | 107 | 119 |
| 2018 | 87 | 85 |
| 2019 | 153 | 53 |
| 2020 | 133 | 58 |
| 2021 | 98 | 76 |
| 2022 | 93 | 112 |
| 2023 | 115 | 68 |
| 2024 | 125 | 70 |
| 2025 | 138 | 57 |
| 2026 | 102 | 12 |
By publication year. 2026 runs to 8 Oct.
Technology areas
Share of 4,491 documents
- G06FComputing and data processing3,296
- G03FPhotomechanical production of textured or patterned surfaces454
- H10DInorganic electric semiconductor devices356
- G01RMeasuring electric variables318
- G11CStatic stores296
- H04LDigital communication217
- H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by175
- H03KPulse technique174
- Y02PLow-carbon manufacturing145
- G06NAI and machine learning141
Recent patents
- Error-correcting and error-detecting parity-check matrix to store a known bad data bit in a memory system29 Sep 2026US 12,748,660 B1
- Statistical graph circuit component probability model for an integrated circuit design29 Sep 2026US 12,748,908 B2
- Low contention high reference offset tolerant level shifter22 Sep 2026US 12,744,532 B1
- Memory data inversion15 Sep 2026US 12,737,138 B1
- Automated multi-stage design flow based on final quality of result15 Sep 2026US 12,737,523 B2
- Memory device with improved sensing margin and leakage immunity24 Sep 2026US 2026/0293078 A1
- Methods and systems for the estimation of the computational cost of simulation17 Sep 2026US 2026/0278215 A1
- Circuitry for Staggering Capture Clocks in Testing Electronic Circuits with Multiple Clock Domains6 Aug 2026US 2026/0227442 A1
- Distributed test pattern generation and synchronization11 Jun 2026US 2026/0160803 A1
- Boolean reasoning guided ungrouping across circuit design hierarchy21 May 2026US 2026/0141147 A1
Most cited
By later US patents
- Segmented channel MOS transistor383US 7,247,887 B22007
- Method and system for layout verification of an integrated circuit design with reusable subdesigns352US 6,009,251 A1999
- Integrated circuit on corrugated substrate310US 7,190,050 B22007
- CAD and simulation system for targeting IC designs to multiple fabrication processes304US 5,754,826 A1998
- Integrated circuit on corrugated substrate274US 7,528,465 B22009