Statistical graph circuit component probability model for an integrated circuit design

A non-transitory computer readable medium comprising stored instructions, which when executed by a processor, cause the processor to:

• receive circuit design training data and circuit design test data, the circuit design training data including training nodes and training paths, wherein the training paths include connect the training nodes including circuit components, and wherein the circuit design test data includes a first test node and a second test node;
• determine testing information for the circuit components of each training path from the circuit design training data;
• determine a statistical representation of the circuit design test data based on the testing information and the circuit design test data;
• and
• determine first test information for a test path connecting the first test node with the second test node based on the statistical representation.

A system comprising:

• a memory storing instructions;
• and
• a processing device, coupled with the memory and configured to execute the instructions, the instructions when executed cause the processing device to:
• receive design training data and design test data, the design training data including training nodes and training paths, wherein the training paths include components and connect the training nodes, and wherein the design test data includes a first test node and a second test node;
• determine testing information for the components of each training path from the design training data, the testing information includes entries including values associated with the components;
• and
• determine test information for a test path connecting the first test node with the second test node based on the entries of the components associated with the test path.