Memory device with improved sensing margin and leakage immunity

A method of fabricating a three-dimensional memory device, comprising:

• providing alternating layers of a first semiconductor material and a second semiconductor material;
• defining first and second transistor regions in the alternating layers of the first and second semiconductor materials, wherein each of the first and second transistor regions are defined on opposite sides of the alternating layers;
• forming a gate on each layer of the first and second transistor regions, the gate including a conductive material;
• forming a capacitor region between each of the first and second transistor regions;
• connecting each of the first transistor regions with a first end of the capacitor region and connecting each of the second transistor regions with a second end of the capacitor region;
• forming bitlines comprising a first bitline connected to a source region in the first transistor region, and a second bitline connected to a source region in the second transistor region;
• and
• forming a wordline connected to the conductive material in each layer of the first and second transistor regions, wherein the wordline provides a common gate control for the first and second transistor regions in each layer.

A three-dimensional memory device, comprising:

• a plurality of memory cells, the plurality of memory cells layered together forms a stack, having a first side and a second side;
• a first bitline and a second bitline, the first bitline along the first side of the stack and the second bitline along the second side of the stack;
• and
• a wordline connecting to each layer of the stack;
• wherein each memory cell comprises:
• a capacitor region comprising a capacitor having a first plate and a second plate, the first plate adjacent to the second plate;
• a first transistor region comprising a first transistor having a channel, a gate terminal connected to a wordline, a source terminal connected to the first bitline, a drain terminal connected to the first plate of the capacitor, one side of the channel connected to the source terminal, and another side of the channel connected to the drain terminal;
• and
• a second transistor region comprising a second transistor having a channel, a gate terminal connected to the wordline, a source terminal connected to the second bitline, a drain terminal connected to the second plate of the capacitor, one side of the channel connected to the source terminal, and another side of the channel connected to the drain terminal;
• wherein the first and second transistor regions are positioned on opposite sides of the capacitor region.