Low contention high reference offset tolerant level shifter
AssigneeSynopsys, Inc.
InventorsAbhishek Roy, Divaker Sharma, Kailash Kumar, Akhil Thotli
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Abstract
A level shifter implemented with contention mitigation is disclosed. The level shifter generally includes: an input transistor pair; a first cascode transistor pair coupled in cascode with the input transistor pair, respectively; first cross-coupled transistors; a second cascode transistor pair coupled in cascode with the first cross-coupled transistors, respectively; a first level shifter transistor pair having gates coupled to drains of the second cascode transistors pair, respectively; and a first contention mitigation transistor pair coupled between a first reference voltage node and the first level shifter transistor pair, respectively.
Claims13
A level shifter, comprising:
- an input transistor pair;
- a first cascode transistor pair coupled in cascode with the input transistor pair, respectively;
- first cross-coupled transistors;
- a second cascode transistor pair coupled in cascode with the first cross-coupled transistors, respectively;
- a first level shifter transistor pair having gates coupled to drains of the second cascode transistors pair, respectively;
- and
- a first contention mitigation transistor pair coupled between a first reference voltage node and the first level shifter transistor pair, respectively, wherein gates of the first contention mitigation transistor pair are coupled to drains of the input transistor pair, respectively.
An input output (IO) device, comprising:
- an IO device transistor;
- a gate driver having an output coupled to a gate of the IO device transistor;
- a level shifter having an output coupled to an input of the gate driver, the level shifter comprising:
- an input transistor pair;
- a first cascode transistor pair coupled in cascode with the input transistor pair, respectively;
- first cross-coupled transistors, wherein a drain of one of the first cross-coupled transistor comprises the output of the level shifter;
- a second cascode transistor pair coupled in cascode with the first cross-coupled transistors, respectively;
- a first level shifter transistor pair having gates coupled to drains of the second cascode transistors pair, respectively;
- and
- a first contention mitigation transistor pair coupled between a first reference voltage node and the first level shifter transistor pair, respectively, wherein gates of the first contention mitigation transistor pair are coupled to drains of the input transistor pair, respectively.
Dependencies are inferred from the claim text.