Method and system for layout verification of an integrated circuit design with reusable subdesigns

A computer system comprising a processor coupled to a bus and a computer readable memory unit coupled to said bus wherein said computer readable memory unit contains instructions stored therein that when executed by said processor cause said computer system to implement a method of verifying the an integrated circuit layout design, said method comprising the steps of:

• a) receiving a stream of layout information representing said integrated circuit layout design, said stream of information comprising a plurality of subcell designs having parent-child relationships;
• b) comparing names of said subcell designs against a history database and parsing and storing into a new database only those subcell designs that are not found within said history database, said history database representing previously parsed subcell designs;
• c) from said new and history databases, constructing a hierarchical tree of said subcell designs from said parent-child relationships;
• d) selecting a selected subcell design from said hierarchical tree;
• e) performing design rule verification on said selected subcell design only if said selected subcell design is not indicated within a validation store;
• f) performing steps d)-e) for each subcell design of said hierarchical tree and generating a design rule verification report on said integrated circuit design layout;
• and
• g) storing into said validation store the geometry of each subcell design selected at step d) that passed design rule verification.

A computer implemented method of verifying an integrated circuit layout design, said method comprising the steps of:

• a) constructing a hierarchical tree of subcell designs from parent-child relationships between said subcell designs, said subcell designs representing said integrated circuit layout design, said step a) comprising the step of comparing names of said subcell designs against a history database and parsing and storing into a new database only those subcell designs that are not found within said history database, said history database representing previously parsed subcell designs;
• b) selecting a selected subcell design from said hierarchical tree;
• c) performing design rule verification and netlist extraction on said selected subcell design only if said selected subcell design is not indicated within a validation store, said netlist extraction generating a netlist of said selected subcell design;
• d) performing steps b)-c) for each subcell design of said hierarchical tree and generating a design rule verification report on said integrated circuit layout design;
• e) storing into said validation store geometry data of each subcell design selected at step b) that passed design rule verification;
• f) selecting a selected subcell design from said hierarchical tree;
• g) using a layout versus schematic checker to compare an extracted netlist corresponding to said selected subcell design to a logical netlist representation of said selected subcell design;
• and
• h) performing steps f)-g) for each subcell design of said hierarchical tree and generating a layout versus schematic verification report on said integrated circuit layout design;
• and
• i) storing into said validation store said extracted netlist of each subdesign selected at step f) that passed layout versus schematic verification.