Memory data inversion
AssigneeSynopsys, Inc.
InventorsHarold Pilo, Anurag Garg
Life of this patent
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Abstract
An example is a circuit including a memory output block having a single bit width output node. The memory output block includes a memory bank and a logic inversion circuit. The memory bank is configured to output a read datum. The logic inversion circuit is associated with the memory bank. An input node of the logic inversion circuit is electrically coupled to the memory bank to receive the read datum. The logic inversion circuit is configured to output an output datum on an output node of the logic inversion circuit. The logic inversion circuit is configured to obtain the output datum by selecting either one of an inverted version of the read datum or a non-inverted version of the read datum received from the memory bank based on a column of the memory bank from which the read datum is read.
Claims20
A circuit comprising:
- a memory output block having a single bit width output node, the memory output block comprising:
- a first memory bank having a first plurality of columns, wherein a first column of the first plurality of columns has a first plurality of memory cells, each memory cell of the first plurality of memory cells being configured to store a respective first stored datum;
- and
- a first logic inversion circuit associated with the first memory bank, an input node of the first logic inversion circuit being electrically coupled to the first memory bank to receive the respective first stored datum,
- wherein the first logic inversion circuit is configured to output a respective first output datum by selecting either one of an inverted version of the respective first stored datum or a non-inverted version of the respective first stored datum for all of the first plurality of memory cells based on the first column of the first memory bank.
A method comprising:
- reading a stored datum from a memory cell in a column of a memory bank, the memory bank having a plurality of columns including the column, wherein the column has a plurality of memory cells including the memory cell, each memory cell of the plurality of memory cells being configured to store a respective stored datum;
- and
- outputting an output datum from a logic inversion circuit electrically coupled to the memory bank comprising selecting either one of an inverted version of the respective stored datum or a non-inverted version of the respective stored datum for all of the plurality of memory cells based on the column of the memory bank.
A non-transitory computer-readable storage medium storing an electronic representation of a circuit design, the circuit design comprising:
- a logic inversion circuit configured to receive on an input node a read datum from a memory bank, the logic inversion circuit comprising column inversion tag circuits, each column inversion tag circuit of the column inversion tag circuits corresponding to a respective column of the memory bank and being configurable to indicate whether to select an inverted version of the read datum or a non-inverted version of the read datum, the logic inversion circuit being configured to obtain an output datum for outputting on an output node of the logic inversion circuit by selecting the inverted version of the read datum or the non-inverted version of the read datum based on a configuration of the respective column inversion tag circuit corresponding to the respective column of the memory bank from which the read datum is read.
Dependencies are inferred from the claim text.