Boolean reasoning guided ungrouping across circuit design hierarchy

A system comprising:

• a memory storing instructions;
• and
• a processor, coupled with the memory and to execute the instructions, the instructions when executed cause the processor to:
• receive a circuit design;
• determine an equivalency metric across a first hierarchy and a second hierarchy from hierarchies of the circuit design, wherein the equivalency metric is based on one or more of a combinational element equivalency and a sequential element equivalency across the first hierarchy and the second hierarch;
• and
• Generate an updated circuit design by ungrouping the first hierarchy of the hierarchies into the second hierarchy of the hierarchies based on the equivalency metric.

A non-transitory computer readable medium comprising stored instructions, which when executed by a processor, cause the processor to:

• receive a circuit design;
• ungroup a first hierarchy to combine into a second hierarchy of the circuit design based on determining whether to use one or more of an XOR parameter, an equivalency metric, and a connectivity parameter,
• wherein the XOR parameter corresponds to a number of XOR equivalent gates within the first hierarchy and the second hierarchy,
• wherein the equivalency metric is based on one or more of a combinational element equivalency and a sequential element equivalency across the first hierarchy and the second hierarchy,
• wherein the connectivity parameter is based on connections between arithmetic operators across the first hierarchy and the second hierarchy;
• and
• generate an updated circuit design based on the ungrouped first hierarchy that is combined into the second hierarchy.