US 5,754,826 A · CAD and simulation system for targeting IC designs to multiple fabrication processes

Abstract

Using the present invention, only a single design and development process needs to be conducted for ICs fabricated using a number of different fabrication processes. In one embodiment of this process, the IC is first designed on a CAD system using a generic Cell Based Architecture (CBA) library. This generic CBA library represents several libraries for different process technologies. The resulting generic design is then simulated and verified using best and worst case timing delays and other parameters which are derived from a combination of the various technologies. Hence, only one design need be created and simulated. Generic design rule and parasitic parameters are then used to optimize the placement and routing of the generic design. The post-layout generic design is then simulated and verified using performance characteristics determined by a combination of the technologies. The accepted, generic post-layout design is then ported for each intended fabrication process to create the mask patterns associated with each fabrication process.

Claims18

Dependent claims

A method for developing an integrated circuit for being fabricated using two or more process technologies, said method comprising the steps of:

providing a generic library of generic macrocells, each of said generic macrocells representing process specific macrocells formed using two or more different process technologies;
designing a generic circuit using said generic macrocells and a generic alignment grid;
simulating said generic circuit using performance characteristics of said process specific macrocells to verify that said generic circuit, when ported to any of said process technologies, would work for its intended purpose;
porting said generic circuit to said two or more process technologies by substituting said generic macrocells in said generic circuit with process specific macrocells and substituting said generic alignment grid with a process specific alignment grid, wherein each generic macrocell location is mapped from its generic reference location on said generic alignment grid to a corresponding process specific macrocell reference location on said process specific alignment grid;
and
creating a set of masks for each of said processes to enable said integrated circuit to be manufactured using said two or more process technologies.

3 more elements

A computer readable storage medium containing a software program for aiding in the development of an integrated circuit for being fabricated using two or more process technologies, said program comprising:

a generic library containing generic macrocells which correspond to logical functions;
a process specific library containing process specific macrocells corresponding to generic macrocells in said generic library;
a set of generic design rules and parameters for placing and routing generic macrocells on a generic alignment grid to carry out performance functions specified by a user of said software;
conversion software for transforming a generic circuit design to a particular process specific circuit design enabling the generic circuit design to be fabricated with a particular process, said generic circuit design comprising said generic macrocells located on said generic alignment grid and being interconnected to carry out desired logical functions, said process specific circuit design comprising said process specific macrocells located on a process specific alignment grid and being interconnected to carry out said desired logical functions, said conversion software substituting said generic macrocells in said generic circuit design with process specific macrocells and substituting said generic alignment grid with a process specific alignment grid, wherein each generic macrocell location is mapped from its generic reference location on said generic alignment grid to a corresponding process specific macrocell reference location on said process specific alignment grid;
and
performance parameters for said process specific macrocells for computation of estimated delay characteristics when said generic circuit is fabricated using said two or more process technologies, enabling the generic circuit design to be simulated and verified to determine whether the final integrated circuit will work for its intended purpose when fabricated using said two or more process technologies.

3 more elements

Dependencies are inferred from the claim text.

CAD and simulation system for targeting IC designs to multiple fabrication processes

Life of this patent

CAD and simulation system for targeting IC designs to multiple fabrication processes

Life of this patent

Abstract

Claims18