Error-correcting and error-detecting parity-check matrix to store a known bad data bit in a memory system

A non-transitory computer-readable medium comprising stored instructions, which when executed by a processor, cause an error correction code (ECC) memory controller to read data stored in a memory, the data comprising a read codeword comprising read system data and read parity data, wherein the stored instructions further cause the ECC memory controller to:

• compute a syndrome based on the read codeword using a parity-check matrix comprising a plurality of columns, wherein a first group of syndromes calculated by the parity-check matrix in a case where the read codeword has a double-bit error and a virtually stored known bad data bit is set and a second group of syndromes calculated by the parity-check matrix in a case where the read codeword has a single-bit error or zero errors are disjoint;
• and
• in a case where the read codeword received has a double bit error and a virtually stored known bad data bit, detect an error in the data and output an indication of detection of the error.