Emulation devices, systems and methods utilizing state machines
AssigneeTexas Instruments Incorporated
InventorsGary L. Swoboda, Martin D. Daniels, Joseph A. Coomes
Life of this patent
Estimating the term…
Abstract
An emulation device including a serial scan testability interface having at least first and second scan paths, and state machine circuitry connected and responsive to said second scan path generally operable for emulation control of logical circuitry associated with said emulation device.
Claims69
An emulation device which enables a functional circuit to support its own emulation, comprising:
- a serial scan testability interface having at least first and second scan paths, said first scan path being provided for applying digital information to the functional circuit for use in emulation of the functional circuit;
- and
- state machine circuitry connected to said second scan path, said state machine circuitry having a sequence of states responsive to said second scan path and corresponding to emulation command codes.
An electronic device, comprising:
- a semiconductor chip with an integrated circuit fabricated thereon, said integrated circuit being provided to support emulation of its own functional operation;
- a serial scan testability interface on-ship having at least first and second scan paths, said first scan path being provided for applying digital information to said integrated circuit for use in emulation of said integrated circuit;
- and
- state machine circuitry on-chip connected to said second scan path, said state machine circuitry having a sequence of states responsive to said second scan path and providing control signals for use in emulation of said integrated circuit.
An electronic system comprising a printed wiring board with serial-scan interconnected electronic devices, at least one of the electronic devices including a semiconductor chip with an integrated circuit fabricated thereon, said at least one electronic device being provided to support emulation of its own functional operation, a serial scan testability interface on-chip having at least first and second scan paths, said first scan path being provided for applying digital information to said at least one of the electronic devices for use in emulation of said at least one of the electronic devices, and said at least one of the electronic devices including state machine circuitry on-chip which is connected to said second scan path, said state machine circuitry having a sequence of states responsive to said second scan path and providing control signals for use in emulation of said at least one of the electronic devices.
An electronic system comprising a host computer, a serial scan interface associated with said host computer for downloading testability codes and emulation command codes, and an electronic system connected to said serial scan interface and including a printed wiring board with at least one electronic device that includes a semiconductor chip with an integrated circuit fabricated thereon, said integrated circuit being provided to support emulation of its own functional operation, a serial scan testability interface on-chip having at least first and second scan paths for receiving said testability codes and emulation command codes respectively, and state machine circuitry on-chip which is connected to said second scan path and which has a sequence of states responsive to said second scan path, wherein said sequence of states provides control signals for use in emulation of said integrated circuit.
A method of operating an emulation device with an integrated circuit which is segmentable into domains and which is provided to support emulation of its own functional operation, comprising the steps of downloading testability codes and emulation command codes to respective scan paths of the integrated circuit and sequentially executing the emulation command codes so that a first command code is executed and then a subsequent emulation command code is executed at a time depending upon completion of a predetermined electronic operation by the integrated circuit wherein at least one domain is operating functionally while at least one domain is operating in accordance with said emulation command codes.
A method of operating an emulation device so as to utilize an integrated circuit in support of its own emulation, comprising the steps of downloading emulation command codes to a scan path of the integrated circuit, the emulation command codes identifying different ones of a plurality of domains of the integrated circuit and which of a test clock and a functional clock is to be applied to each domain, and executing the emulation command codes to couple the test clock or the functional clock to the domains of the integrated circuit in accordance with the emulation command codes.
An electronic device, comprising:
- a semiconductor chip having an integrated circuit fabricated thereon;
- said integrated circuit including functional circuitry for performing normal operating functions of said integrated circuit, said auxiliary circuitry for performing auxiliary functions that provide information regarding the machine state of said functional circuitry, said auxiliary circuitry including state machine circuitry having an input which is accessible externally of said integrated circuit for permitting external control of said auxiliary functions;
- said auxiliary circuitry further including a test architecture operatively associated with said functional circuitry and capable of executing operations according to a test methodology, said test architecture having a control interface through which said test architecture is controllable, said control circuitry being embedded within said integrated circuit;
- and
- said auxiliary circuitry further including adaptor circuitry interfacing between said state machine circuitry and said test architecture, said adaptor circuitry including a serial scan path for receiving data selected by said state machine circuitry, said adaptor circuitry also including circuitry responsive to said state machine circuitry and said data in said serial scan path for selectively operating said embedded control interface of said test architecture.
An electronic system, comprising:
- a semiconductor chip having an integrated circuit fabricated thereon:
- said integrated circuit having functional circuitry for performing normal operating functions of said integrated circuit, said auxiliary circuitry for performing auxiliary functions that provide information regarding the machine state of said functional circuitry, said auxiliary circuitry including state machine circuitry having an input which is accessible externally of said integrated circuit for permitting external control of said auxiliary functions;
- said auxiliary circuitry further including a test architecture operatively associated with said functional circuitry and capable of executing operations according to a test methodology, said test architecture having a control interface through which said test architecture is controllable, said control interface being embedded within said integrated circuit;
- said auxiliary circuitry further including adaptor circuitry interfacing between said state machine circuitry and said test architecture, said adaptor circuitry including a serial scan path for receiving data selected by said state machine circuitry, said adaptor circuitry also including circuitry responsive to said state machine circuitry and said data in said serial scan path for selectively operating said embedded control interface of said test architecture;
- and
- wherein said electronic system includes a plurality of said semiconductor chips, said externally accessible inputs of said state machine circuitries being connected together to form a common externally accessible input, and said serial scan paths being connected together in series.
A method of evaluating the functionality of an integrated circuit, comprising the steps of:
- providing within the integrated circuit a test architecture capable of executing operations according to a test methodology;
- embedding a control interface of the test architecture within the integrated circuit;
- providing state machine circuitry within the integrated circuit;
- accessing the state machine circuitry externally of the integrated circuit to select a serial scan path provided in the integrated circuit;
- scanning data into the selected serial scan path;
- and
- selectively operating the embedded control interface of the test architecture in response to operation of the state machine circuitry and to the data in the serial scan path.
Dependencies are inferred from the claim text.