G01R 31/318541
Scan latches or cell details
Official title: {Scan latches or cell details}
G01R31/318541 (Scan latches or cell details) appears on 792 US grants and 642 published applications in this corpus.
Search patents in G01R- Granted patents
- 792
- Published applications
- 642
- Assignees
- 197
- Inventors
- 1,240
- Latest grant
- 15 Sep 2026
Filings by year
| Year | Granted patents | Published applications |
|---|---|---|
| 1977 | 2 | 0 |
| 1978 | 1 | 0 |
| 1979 | 0 | 0 |
| 1980 | 0 | 0 |
| 1981 | 2 | 0 |
| 1982 | 0 | 0 |
| 1983 | 0 | 0 |
| 1984 | 1 | 0 |
| 1985 | 2 | 0 |
| 1986 | 6 | 0 |
| 1987 | 8 | 0 |
| 1988 | 3 | 0 |
| 1989 | 5 | 0 |
| 1990 | 1 | 0 |
| 1991 | 5 | 0 |
| 1992 | 7 | 0 |
| 1993 | 2 | 0 |
| 1994 | 9 | 0 |
| 1995 | 15 | 0 |
| 1996 | 13 | 0 |
| 1997 | 13 | 0 |
| 1998 | 19 | 0 |
| 1999 | 15 | 0 |
| 2000 | 11 | 0 |
| 2001 | 16 | 2 |
| 2002 | 16 | 16 |
| 2003 | 18 | 32 |
| 2004 | 20 | 29 |
| 2005 | 22 | 25 |
| 2006 | 21 | 29 |
| 2007 | 29 | 32 |
| 2008 | 30 | 34 |
| 2009 | 28 | 14 |
| 2010 | 32 | 21 |
| 2011 | 27 | 29 |
| 2012 | 18 | 23 |
| 2013 | 30 | 29 |
| 2014 | 31 | 31 |
| 2015 | 34 | 30 |
| 2016 | 35 | 37 |
| 2017 | 35 | 31 |
| 2018 | 26 | 20 |
| 2019 | 36 | 16 |
| 2020 | 14 | 21 |
| 2021 | 21 | 25 |
| 2022 | 27 | 15 |
| 2023 | 23 | 23 |
| 2024 | 26 | 35 |
| 2025 | 21 | 27 |
| 2026 | 16 | 16 |
By publication year. Applications have been published since 2001. 2026 runs to 8 Oct.
Recent patents
- High performance data latching using an energy efficient clocked latch topology15 Sep 2026US 12,738,929 B2International Business Machines Corporation
- Integrated circuit including constant-0 flip flops reconfigured to provide observable and controllable test points25 Aug 2026US 12,716,944 B2QUALCOMM Incorporated
- Secure scan testing of integrated circuits25 Aug 2026US 12,716,945 B2SK hynix Inc.
- Integrated-circuit chip for retention cell testing23 Jun 2026US 12,663,469 B2Nordic Semiconductor ASA
- Integrated circuit with multiplexer for testing16 Jun 2026US 12,656,397 B2Samsung Electronics Co., Ltd.
- Efficient scannable register file cell with low overhead3 Sep 2026US 2026/0259262 A1International Business Machines Corporation
- Scan Operation Methods and Devices27 Aug 2026US 2026/0251708 A1Arm Limited
- Memory device configured for detecting a connection failure between signal paths27 Aug 2026US 2026/0251712 A1SK hynix Inc.
- Semiconductor integrated circuit20 Aug 2026US 2026/0243823 A1Canon Kabushiki Kaisha
- Scan Flip-Flops With Pre-Setting Combinational Logic13 Aug 2026US 2026/0235676 A1Taiwan Semiconductor Manufacturing Company.Ltd
Most cited
By later US patents
- Structure and method for producing mask-programmed integrated circuits which are pin compatible substitutes for memory-configured logic arrays223US 5,068,603 AXilinx, Inc. · 1991
- Use of a scan chain for configuration of BIST unit operation104US 6,574,762 B1LSI Logic Corporation · 2003
- Self-configurable circuit structure for achieving wafer scale integration103US 4,038,648 A1977
- Fast scan/set testable latch using two levels of series gating with two current sources88US 4,580,066 ASperry Corporation · 1986
- System for scan testing of logic circuit networks88US 4,855,669 AXilinx, Inc. · 1989