Fast scan/set testable latch using two levels of series gating with two current sources

An addition improvement to the apparatus of feedback latch circuit employing two levels of series gating and one current source to the end that such latch circuit should be made scan/set testable responsively to received scan/set data, scan/set clock, and scan/set enablement signals, said improvement comprising:

• current source means for supplying a current;
• first current switch means collector dotted connected with each one of the set Q and clear Q signal outputs of said feedback latch circuit for, IF supplied with a current, THEN, responsively to the binary state of a received said scan/set data signal, switching said current either to said set Q or to said clear Q signal outputs as said binary state of said scan/set data signal dictates, in order by said current switching to said set Q or to said clear Q signal outputs respectively either to clear or to set said feedback latch circuit, despite such feedback currents as therein exist, ELSE IF not supplied with a current, THEN conducting no current to either said set Q or said clear Q signal outputs and presenting but a small capacitance to each said set Q and said clear Q signal outputs:
• second current switch means connected intermediary said current source means and said first current switch means for, responsively to the binary state of a control signal, IF said control signal is true THEN switching said current supplied be said current source means to said first current switch means ELSE IF said control signal is false, THEN switching said current supplied by said current source means toward ground;
• and
• scan/set test control means for, IF both a received said scan/set clock signal and said scan/set enablement signal exist in the true condition, THEN providing the true state of said control signal to said second current switch means, ELSE IF either said scan/set clock signal or said scan/set enablement signal or both exist in the false condition, THEN providing the false state of said control signal to said second current source means.