US 12,716,945 B2 · Secure scan testing of integrated circuits

Abstract

Techniques for scan testing integrated circuits that process sensitive data while protecting such data from unauthorized access. A second scan register is provided in parallel to a primary scan register, the second scan register functionally replicating the primary scan register. The primary and replica scan registers are scan loadable (i.e., can be loaded with scan data) but are non-scannable (i.e., not scan readable). Instead of data captured by the first and second scan registers being scanned out for external observation, contents of the first and second scan registers are compared, and the comparison result is captured by a third scan register that operates as a regular scannable (or scan readable) register. The values of the third scan register scanned out for observation reflect the test results, and data in the first and second scan registers are not scanned out and cannot be observed.

Claims20

Dependent claims

A method for secure scan testing an integrated circuit comprising:

receiving a first test pattern;
loading the first test pattern into a first non-scannable scan register and a second non-scannable scan register, the second non-scannable scan register substantially functionally replicating the first non-scannable scan register;
activating a part of the integrated circuit associated with the first non-scannable scan register in response to the loaded first test pattern;
capturing a response of the part of the integrated circuit associated with the first non-scannable scan register in the first non-scannable scan register and the second non-scannable scan register;
comparing contents of the first non-scannable scan register with contents of the second non-scannable scan register to generate a compare result;
capturing the compare result in a scannable scan register;
and
scanning out contents of the scannable scan register for observation by test equipment,
wherein contents of the first non-scannable scan register and the second non-scannable scan register are not scanned out, thereby remaining secure.

6 more elements

An integrated circuit comprising:

circuitry configured to perform logic functions;
a first non-scannable scan register associated with the circuitry and configured to receive, in a first cycle, a test pattern at an input, and to receive, in a second cycle, responses to the test pattern from the circuitry;
a second non-scannable scan register substantially functionally replicating the first non-scannable scan register, associated with the circuitry and configured to receive, in the first cycle, the test pattern at an input, and to receive, in the second cycle, the responses to the test pattern from the circuitry;
a compare circuit coupled to the first non-scannable scan register and the second non-scannable scan register, the compare circuit configured to:
compare a data bit from the first non-scannable scan register to a corresponding data bit from the second non-scannable scan register, and
generate a result of the comparison;
and
a scannable scan register having an input coupled to the compare circuit and an output, the scannable scan configured to receive the result of the comparison and to scan out its content at the output,
wherein contents of the first non-scannable scan register and the second non-scannable scan register are not scanned out and remain secure.

6 more elements

Dependencies are inferred from the claim text.

Secure scan testing of integrated circuits

Life of this patent

Secure scan testing of integrated circuits

Life of this patent

Abstract

Claims20