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US 4,855,669 AGranted
System for scan testing of logic circuit networks
AssigneeXilinx, Inc.
InventorJohn E. Mahoney
Life of this patent
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Abstract
The integrity of a circuit processing logic signals is verified by use of switching means, including pass transistors, which are selectively varied to provide different test circuit configurations for different modes of operation. The circuit operates in normal, scan, test and data receive modes. During normal operation, the logic signal from the primary circuit is passed directly through a logic test block without the shifting of data in the logic test block.
Claims14
A test block structure for scan testing a network of digital logic blocks, the test block structure comprising:
- a first input node for receiving a first digital input signal,
- a first output node for outputting a first digital output signal;
- first switch means for selectively connecting said first input node to said first output node, the first switch means including first and second signal conducting portions for conducting signals through the first switch means;
- a second input node for receiving a second digital input signal;
- a second output node for outputting a second digital output signal;
- data storage means, having an input terminal and an output terminal, for storing digital data received at the input terminal thereof from either of the first and second input nodes and for outputting the stored digital data through the output terminal thereof, said output terminal being connected to the second output node,
- second switch means for selectively connecting the input terminal of the storage means to the second input node;
- third switch means for selectively connecting said first input node to the input terminal of said data storage means, the third switch means being integrally formed with the first signal conducting portion such that signals passing through the third switch means must pass through the first signal conducting portion;
- and
- fourth switch means for selectively connecting the output terminal of said data storage means to said first output node, the fourth switch means being integrally formed with the second signal conducting portion such that signals passing through the fourth switch means must pass through the second signal conducting portion.
7 more elements
A digital logic test block for scan testing a network of digital logic circuits, comprising:
- a primary input node for receiving first primary data from one of the digital logic circuits of said network;
- an auxiliary input node for receiving first auxiliary data;
- a primary output node for outputting primary output node data to another of the digital logic circuits of said network;
- an auxiliary output node for outputting second auxiliary output node data;
- digital storage means for storing input data received at either of the primary and auxiliary input nodes, the storage means having an input line for receiving the input data and an output line for outputting stored data;
- first switching means for selectively connecting the input line of the storage means to one of the primary and auxiliary input nodes, the first switching means including a first signal conducting portion for conducting signals between the primary input node and the storage means input line;
- and
- second switching means for selectively connecting the primary output node to one of the primary input node and the output line of the digital storage means, the second switching means having a first signal conducting portion being adjoined to the first signal conducting portion of the first switching means such that the second switching means shares the first signal conducting portion with the first switching means and such that verification of signal conduction through the first switching means, from the primary input node to the input line of the storage means, assures the integrity of the first signal conducting portion of the second switching means.
5 more elements
Dependencies are inferred from the claim text.