Structure and method for producing mask-programmed integrated circuits which are pin compatible substitutes for memory-configured logic arrays

A metal-interconnected integrated circuit chip to be substituted for a pass-transistor-interconnected integrated circuit chip, the latter chip having plural pass transistors each characterized by a first signal transmission delay, the metal-interconnected integrated circuit chip being pin compatible with the latter chip and comprising:

• plural resistive routing lines for routing signals previously routed by the pass transistors of the latter chip, each of the resistive routing lines being characterized by one or more segments having second signal transmission delays approximately equal, within an order of magnitude, to the first signal transmission delay;
• first and second logic function blocks each having input and output terminals;
• and
• a scan test block having:
• (a) a primary input terminal connected to the output terminal of the first logic function block,
• (b) a primary output terminal connected to the input terminal of the second logic function block,
• (c) a scan-in terminal for receiving scan path signals,
• (d) a scan-out terminal for outputting scan path signals,
• (e) first through fourth signal conducting nodes,
• (f) first switch means for selectively connecting the scan-in terminal to the first signal conducting node,
• (g) digital data storing means, having an input section coupled to the first signal conducting node and an output section coupled to the fourth signal conducting node, the digital data storing means being provided for storing data transmitted through the first signal conducting node and for outputting stored data through the fourth signal conducting node,
• (h) second switch means, integrally formed of the first and second signal conducting nodes, for selectively connecting the first and second signal passing nodes,
• (i) third switch means, integrally formed of the second and third signal conducting nodes, for selectively connecting the second and third signal passing nodes, and
• (j) fourth switch means, integrally formed of the third and fourth signal conducting nodes, for selectively connecting the third and fourth signal passing nodes;
• wherein the primary input terminal is coupled to the second signal conducting node, the primary output terminal is coupled to the third signal conducting node, the scan-out terminal is coupled to the fourth signal conducting node.