Scan Flip-Flops With Pre-Setting Combinational Logic

A scan flip-flop device comprising:

• a scan flip-flop circuit;
• and
• a pre-setting combinational logic circuit coupled to the scan flip-flop circuit and configured to, based on one or more control signals, override and pre-set a scan-related signal to a known logic value, wherein the scan flip-flop device is operable:
• in a front-end arrangement in which the scan-related signal includes a pre-set scan input for the scan flip-flop circuit;
• or
• in a back-end arrangement in which the scan-related signal includes a pre-set output generated based on an output of the scan flip-flop circuit.

A method of testing a scan chain, the method comprising:

• pre-setting, using one or more control signals applied to a pre-setting combinational logic circuit, a scan-related signal associated with a scan flip-flop of a scan chain to a known logic value, wherein the scan chain includes a plurality of scan flip-flops coupled in series;
• capturing data in the scan chain responsive to one or more clock transitions;
• and
• scanning out a bit stream from the scan chain and comparing the bit stream with an expected bit stream corresponding to the known logic value to identify a malfunctioning scan flip-flop in the scan chain.