G01R 31/318544
Scanning methods, algorithms and patterns
Official title: {Scanning methods, algorithms and patterns (G01R31/3183 takes precedence)}
G01R31/318544 (Scanning methods, algorithms and patterns) appears on 1,256 US grants and 1,082 published applications in this corpus.
Search patents in G01R- Granted patents
- 1,256
- Published applications
- 1,082
- Assignees
- 261
- Inventors
- 1,636
- Latest grant
- 25 Aug 2026
Filings by year
| Year | Granted patents | Published applications |
|---|---|---|
| 1976 | 1 | 0 |
| 1977 | 0 | 0 |
| 1978 | 0 | 0 |
| 1979 | 0 | 0 |
| 1980 | 1 | 0 |
| 1981 | 1 | 0 |
| 1982 | 1 | 0 |
| 1983 | 0 | 0 |
| 1984 | 1 | 0 |
| 1985 | 6 | 0 |
| 1986 | 4 | 0 |
| 1987 | 6 | 0 |
| 1988 | 6 | 0 |
| 1989 | 4 | 0 |
| 1990 | 6 | 0 |
| 1991 | 2 | 0 |
| 1992 | 4 | 0 |
| 1993 | 6 | 0 |
| 1994 | 8 | 0 |
| 1995 | 18 | 0 |
| 1996 | 9 | 0 |
| 1997 | 17 | 0 |
| 1998 | 18 | 0 |
| 1999 | 13 | 0 |
| 2000 | 10 | 0 |
| 2001 | 9 | 3 |
| 2002 | 15 | 21 |
| 2003 | 28 | 40 |
| 2004 | 32 | 44 |
| 2005 | 26 | 56 |
| 2006 | 43 | 64 |
| 2007 | 58 | 62 |
| 2008 | 49 | 62 |
| 2009 | 60 | 52 |
| 2010 | 67 | 64 |
| 2011 | 73 | 48 |
| 2012 | 45 | 44 |
| 2013 | 59 | 45 |
| 2014 | 57 | 71 |
| 2015 | 73 | 66 |
| 2016 | 67 | 53 |
| 2017 | 54 | 42 |
| 2018 | 53 | 51 |
| 2019 | 51 | 26 |
| 2020 | 32 | 21 |
| 2021 | 35 | 27 |
| 2022 | 26 | 25 |
| 2023 | 36 | 28 |
| 2024 | 29 | 30 |
| 2025 | 22 | 19 |
| 2026 | 15 | 18 |
By publication year. Applications have been published since 2001. 2026 runs to 8 Oct.
Subgroups
Granted patents
Recent patents
- Secure scan testing of integrated circuits25 Aug 2026US 12,716,945 B2SK hynix Inc.
- Wrapper cell design and built-in self-test architecture for 3DIC test and diagnosis21 Jul 2026US 12,687,578 B2Taiwan Semiconductor Manufacturing Company.Ltd
- Infield periodic device testing while maintaining host connectivity14 Jul 2026US 12,681,085 B2Intel Corporation
- Architecture for testing multiple scan chains30 Jun 2026US 12,669,541 B2STMicroelectronics International N. V.
- Processor test pattern generation and application for tester systems26 May 2026US 12,638,501 B2Advantest Corporation
- Wrapper Cell Design and Built-In Self-Test Architecture for 3DIC Test and Diagnosis8 Oct 2026US 2026/0309778 A1Taiwan Semiconductor Manufacturing Company.Ltd
- Integrated circuit margin measurement for structural testing3 Sep 2026US 2026/0259261 A1Proteantecs Ltd.
- Memory device configured for detecting a connection failure between signal paths27 Aug 2026US 2026/0251712 A1SK hynix Inc.
- Select gate scan using double verify20 Aug 2026US 2026/0243822 A1Micron Technology, Inc.
- Semiconductor device and method of inspecting semiconductor device13 Aug 2026US 2026/0235675 A1Canon Kabushiki Kaisha
Most cited
By later US patents
- Method to locate logic errors and defects in digital circuits273US 7,296,201 B2DAFCA, Inc. · 2007
- Structure and method for producing mask-programmed integrated circuits which are pin compatible substitutes for memory-configured logic arrays223US 5,068,603 AXilinx, Inc. · 1991
- Arithmetic built-in self test of multiple scan-based integrated circuits174US 5,991,898 AMentor Graphics Corporation · 1999
- Simultaneous self-testing system167US 4,513,418 AInternational Business Machines Corporation · 1985
- Method and apparatus for evaluating and optimizing a signaling system146US 7,490,275 B2Rambus Inc. · 2009