Architecture for testing multiple scan chains

A method for serially testing N number of finite state machine circuits using N number of scan chains, where N is an integer greater than one, each scan chain coupled to a finite state machine circuit to test the finite state machine circuit coupled thereto, each scan chain having M number of input terminals and one output terminal, where M is an integer greater than one, the method comprising:

• receiving two or more consecutive logic level low shift enable signals or reset signals to initiate a configuration mode of a dispatcher input interface, the dispatcher input interface comprising:
• a plurality of flip-flops arranged in series, wherein an output of each flip-flop other than a last flip-flop is coupled to a data input of a next flip-flop and a clock terminal of each flip-flop is coupled to a clock signal, wherein the plurality of flip-flops is configured to detect two or more consecutive logic level low shift enable signals or reset signals to initiate a configuration mode of the dispatcher input interface,
• a plurality of AND gates coupled to each other and the plurality of flip-flops, wherein the plurality of AND gates is configured to generate a dispatch enable signal based on outputs of the plurality of the flip-flops, the dispatch enable signal indicating entry into the configuration mode,
• M number of input terminals, and
• N sets of output terminals, each of the N sets of output terminals comprising M number of output terminals coupled to the M number of input terminals of an associated scan chain;
• receiving a test input signal indicating the scan chain to be selected for testing the finite state machine circuit coupled to the scan chain;
• and
• receiving one or more logic level high shift enable signals or reset signals to end the configuration mode of the dispatcher input interface.

A device, comprising:

• N number of asynchronous finite state machine circuits, where N is an integer greater than one;
• N number of scan chains, each scan chain coupled to an asynchronous finite state machine circuit to test the asynchronous finite state machine circuit coupled thereto, each scan chain having M number of input terminals and one output terminal, where M is an integer greater than one;
• a dispatcher input interface comprising:
• a plurality of flip-flops arranged in series, wherein an output of each flip-flop other than a last flip-flop is coupled to a data input of a next flip-flop and a clock terminal of each flip-flop is coupled to a clock signal, wherein the plurality of flip-flops is configured to detect two or more consecutive logic level low shift enable signals or reset signals to initiate a configuration mode of the dispatcher input interface,
• a plurality of AND gates coupled to each other and the plurality of flip-flops, wherein the plurality of AND gates is configured to generate a dispatch enable signal based on outputs of the plurality of the flip-flops, the dispatch enable signal indicating entry into the configuration mode,
• M number of input terminals, and
• N sets of output terminals, each of the N sets of output terminals comprising M number of output terminals coupled to the M number of input terminals of an associated scan chain;
• and
• a dispatcher output interface having N number of input terminals and one output terminal, wherein the output terminal of each scan chain is coupled to one of the N number of input terminals of the dispatcher output interface.